An Efficient Dual-Channel Data Storage and Access Method for Spaceborne Synthetic Aperture Radar Real-Time Processing

Abstract

With the development of remote sensing technology and very large-scale integrated circuit (VLSI) technology, the real-time processing of spaceborne Synthetic Aperture Radar (SAR) has greatly improved the ability of Earth observation. However, the characteristics of external memory have led to matrix transposition becoming a technical bottleneck that limits the real-time performance of the SAR imaging system. In order to solve this problem, this paper combines the optimized data mapping method and reasonable hardware architecture to implement a data controller based on the Field-Programmable Gate Array (FPGA). First of all, this paper proposes an optimized dual-channel data storage and access method, so that the two-dimensional data access efficiency can be improved. Then, a hardware architecture is designed with register manager, simplified address generator and dual-channel Double-Data-Rate Three Synchronous Dynamic Random-Access Memory (DDR3 SDRAM) access mode. Finally, the proposed data controller is implemented on the Xilinx XC7VX690T FPGA chip. The experimental results show that the reading efficiency of the data controller proposed is 80% both in the range direction and azimuth direction, and the writing efficiency is 66% both in the range direction and azimuth direction. The results of a comparison with the recent implementations show that the proposed data controller has a higher data bandwidth, is more flexible in its design, and is suitable for use in spaceborne scenarios.

An Efficient On-Chip Data Storage and Exchange Engine for Spaceborne SAR System

“…where t CK is the DDR3 chip's working clock period; t RCD is the interval delay time between when the row activation command is valid and when the read or write command activation is valid; the delay from the effective write command to the effective write data is called t CW L ; the time from the completion of the write operation to the pre-charging is called t WR ; t RP represents the delay time between pre-charging and the activation of the next row; t RTP represents the time interval between the read data command and the pre-charging [35].…”

“…In the paper [35], the system pipeline is a scalar pipeline, that is, when data are accessed, the data are read from DDR3A and transmitted to the processing engine for processing. When the processed data are written into DDR3B, DDR3A reads the next data in the range direction or azimuth direction for processing.…”

“…The scalar pipeline is more efficient than the no-pipeline design, but the long data processing time in the SAR imaging system causes the pipeline to generate a waiting or blocking state, which has an effect on real-time system processing. The range and azimuth read and write efficiency and bandwidth in the paper [35] are summarized in Table 2.…”

“…Sun et al [34] balanced the range and azimuth accesses efficiency using a matrix block cross-mapping method. Wang et al [35] used a dual-channel pipeline design to implement balanced two-dimensional access efficiency, higher buffer RAM utilization, and improved data exchange efficiency.…”

On-Board Geometric Rectification for Micro-Satellite Based on Lightweight Feature Database

“…Embedded on-board processing systems generally fall into three categories: Digital Signal Processors (DSPs), Field-Programmable Gate Arrays (FPGA), and Graphics Processing Units (GPUs). Traditional on-board processing methods primarily revolve around FPGA utilization, involving the adaptation of algorithms to suit hardware characteristics [8,12,21] and designing specific FPGA implementations tailored to particular algorithms [22][23][24][25]. However, DSP and FPGA platforms have their drawbacks, including obsolescence, rigidity, and high costs [5].…”