An Efficient Optimization Based Method to Evaluate the DRV of SRAM Cells

Huang, Guanming; Qian, Liuxi; Saibua, Siwat; Zhou, Dian; Zeng, Xuan

doi:10.1109/tcsi.2012.2226504

Cited by 25 publications

(5 citation statements)

References 17 publications

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“…Mohana chandrika and Siva Kumar (2022) designed the SRAM cell using using reversible logic gates sensible portable gates for smart computer devices. Huang et al (2013) give a novel approach to find the DRV of SRAM memory when changing parameters. Alluri et al (2020) have designed CMOS circuit which gives the better performance in term of power and speed.…”

Section: Literature Reviewmentioning

confidence: 99%

Design and Analysis of SRAM Cell for Smart Application

Praveen¹,

Singh²

2022

Journal of Computer Science

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In today's circuit technology, power consumption and savings are key concerns. The driving reasons behind these innovations are portable devices that require high throughput and low power dissipation, such as computers, phones, and Personal Digital Assistants (PDAs). In portable devices, reducing or decreasing IC dissipated power through design optimization is a big problem, and restricted battery lifespan places very severe restrictions on overall power usage. In this study SRAM circuit for smart applications has been investigated using various factors such as write, read, dynamic, static power with voltage and temperature. The power consumption analysis is the most essential criteria for memory design. Because data stability is a critical concern, affecting both the read and write operations. The implemented 9T SRAM in this study is more efficient than the other SRAM in terms of power usage. When compared with the existing SRAM circuits taken for comparison of different parameters, the proposed 9T SRAM, circuit uses less than 28.2% write power, while it uses about the same for read operation. The data retention voltage for both circuits is 0.29 V, which is utilized to store the data in the circuit. The 32 nm Bulk CMOS process technology from PTM files is used for designing and analysis.

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Section: Literature Reviewmentioning

confidence: 99%

Design and Analysis of SRAM Cell for Smart Application

Praveen¹,

Singh²

2022

Journal of Computer Science

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“…The second observation driving our approach is that after a system ceases computation due to power failure, the remanent charge keeps the device's voltage higher than SRAM's Data Retention Voltage (DRV) for some time. This is because SRAM DRV, which is ∼0.4V [16,43], is much lower than the operational voltage of the microcontroller (e.g., 1.6V for the representative MSP430s). When supply voltage falls below the minimum operating voltage of the microcontroller, the power consumption drops drastically as transistors stop switching; power drain is now dominated by leakage current in the MCU and surrounding circuitry.…”

Section: Sram Has Time-dependent Volatilitymentioning

confidence: 99%

Forget Failure

Williams

Jian

Hicks

2020

Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Syste

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Energy harvesting is a promising solution to power billions of ultra-low-power Internet-of-Things devices to enable ubiquitous computing. However, energy harvesters typically output tiny amounts of energy and, therefore, cannot continuously power devices; this leads to intermittent computing, where the energy harvester periodically charges a capacitor to sufficient voltage to power brief computation, until the capacitor's charge is drained, and the cycle repeats. To retain program state across frequent power failures, prior work proposes checkpointing program state to Non-Volatile Memory (NVM) before a power failure. Unfortunately, the most widely deployed, highest performance, and lowest cost devices employ Flash as their NVM, but the power, time, and endurance limitations of Flash writes are incompatible with the frequent NVM checkpoints of intermittent computation.The multi-year data retention of Flash is overkill for retaining program state across intermittent computing's short power-off times (e.g., <1s). We observe that even after computation stops due to low voltage, charge remains in the system; this remaining charge keeps the voltage high enough to maintain data in SRAM-effectively making it a NVM-for 10's of minutes post-power loss. This paper explores how to leverage SRAM's data remanence to boost common-case performance and energy efficiency for Flash-based intermittent computation systems. We propose TotalRecall, a library-level, in-situ, checkpointing technique that retains program state in SRAM and identifies when SRAM acts as a NVM, falling back to conventional NVM checkpoints in the rare event of long off times. Our evaluation, on real hardware, using benchmarks from Texas Instruments, shows that TotalRecall incurs overheads as low as 0.8%-up to over 350x faster than checkpointing to Flash.

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“…Postfabrication methods are also developed which uses canary replica cells [14,15] and builtin self-test [16,17] to obtain DRV. However, the optimization based method proposed by G. Huang et al [18] has been claimed to be the fastest evaluation method to obtain DRV. He formulated DRV as a time domain worst performance bound problem and then multistart point (MSP) optimization strategy is developed to evaluate the failure bound.…”

Section: Introductionmentioning

confidence: 99%

DRV Evaluation of 6T SRAM Cell Using Efficient Optimization Techniques

Joshi

Nayak

2018

Active and Passive Electronic Components

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An optimization based method which uses bisection search algorithm has been proposed to evaluate the accurate value of Data Retention Voltage (DRV) of a 6T Static Random Access Memory (SRAM) cell using 45 nm technology in the presence of process parameter variations. Further, we incorporate an Artificial Neural Network (ANN) block in our proposed methodology to optimize the simulation run time. The highest values obtained from these two methods are declared as the DRV. We noted an increase in DRV with temperature (T) and process variations (PVs). The main advantage of the proposed technique is to reduce the DRV evaluation time and for our case, we observe improvement in evaluation time of DRV by ≈46, ≈27, and ≈8 times at 25°C for 3 σ, 4 σ, and 5 σ variations, respectively, using ANN block to without using ANN block.

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An Efficient Optimization Based Method to Evaluate the DRV of SRAM Cells

Cited by 25 publications

References 17 publications

Design and Analysis of SRAM Cell for Smart Application

Design and Analysis of SRAM Cell for Smart Application

Forget Failure

DRV Evaluation of 6T SRAM Cell Using Efficient Optimization Techniques

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