Forget Failure

Abstract

Energy harvesting is a promising solution to power billions of ultra-low-power Internet-of-Things devices to enable ubiquitous computing. However, energy harvesters typically output tiny amounts of energy and, therefore, cannot continuously power devices; this leads to intermittent computing, where the energy harvester periodically charges a capacitor to sufficient voltage to power brief computation, until the capacitor's charge is drained, and the cycle repeats. To retain program state across frequent power failures, prior work proposes checkpointing program state to Non-Volatile Memory (NVM) before a power failure. Unfortunately, the most widely deployed, highest performance, and lowest cost devices employ Flash as their NVM, but the power, time, and endurance limitations of Flash writes are incompatible with the frequent NVM checkpoints of intermittent computation.The multi-year data retention of Flash is overkill for retaining program state across intermittent computing's short power-off times (e.g., <1s). We observe that even after computation stops due to low voltage, charge remains in the system; this remaining charge keeps the voltage high enough to maintain data in SRAM-effectively making it a NVM-for 10's of minutes post-power loss. This paper explores how to leverage SRAM's data remanence to boost common-case performance and energy efficiency for Flash-based intermittent computation systems. We propose TotalRecall, a library-level, in-situ, checkpointing technique that retains program state in SRAM and identifies when SRAM acts as a NVM, falling back to conventional NVM checkpoints in the rare event of long off times. Our evaluation, on real hardware, using benchmarks from Texas Instruments, shows that TotalRecall incurs overheads as low as 0.8%-up to over 350x faster than checkpointing to Flash.

Automatically enforcing fresh and consistent inputs in intermittent systems

“…Third, prior timeliness techniques add extra time-keeping hardware: a low-power real-time clock [20,27] or a timekeeper based on charge remanence [15,45,56]. The need for time-keeping hardware precludes the adoption of these techniques on unmodified platforms.…”

“…TICS [27] is most similar to this work, providing timely intermittent computation through annotations on existing programs. In contrast to Ocelot, both these works require reasoning about real-time, do not examine temporal-consistency, and require additional hardware to keep time through power failures [15,56]. TICS also presents an architecture for constant-time checkpoints, which is complementary and can be used with Ocelot.…”

“…Most prior efforts focus primarily on problems related to progress and memory consistency. To save state, these techniques rely on in-code checkpointing (or tasks) [11, 31ś33, 46, 48, 53, 57], or rely on a dynamic "just-in-timež (JIT) checkpointing mechanism [2,3,15,23,34,35,37,56] that captures a snapshot of volatile state just before power fails.…”