An efficient list-based scheduling algorithm for high-level synthesis

Sllame, Azeddien M.; Drabek, V.

doi:10.1109/dsd.2002.1115384

Cited by 26 publications

(15 citation statements)

References 15 publications

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“…The purpose of using different priority functions with a list-based scheduling algorithm is to further explore the underlying structure of the schedules produced by each selection method employed in those priority functions. For instance, the priority functions mobility+tree-structuring and mobility+treeid+ same successor are able to produce efficient structured schedules, as seen in [12]. The output of this exploration step is a set of tables comparing different results of distinct allocated resource sets with different scheduling algorithms.…”

Section: The Incorporated Methodologymentioning

confidence: 98%

“…the calculation of the computation path length including the node toward the DFG input nodes, since the selection of the resource set is made before the pipelining process [10]. The forward approach priority function is based on the mobility as a main priority function plus a graph construction technique presented in [12] as a secondary priority function. In short, a tree-like structure is constructed in the pre-processing phase in such a way that the underlying DFG structure of the design behavior is well captured and used to guide the scheduler to select the proper operation to be scheduled in the current cstep, in efficient computational time.…”

Section: The Incorporated Methodologymentioning

confidence: 99%

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EVO-EXPLORER: A Tool for Designing High-Performance Digital Systems

Sllame

2007

2007 Innovations in Information Technologies (IIT)

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In this paper we describe a toolfor designing highperformance digital systems. The system is described behaviorally in VHDL and then translated into data flow graph (DFG) structure which captures all control and data flow dependencies of the given behavioral description. Then the design process goes through architecture selection, scheduling, pipelining and component selection processes. As it enters each step, it is explored by a local exploration scheme. The set of developed algorithms tested with standard benchmarks.

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Section: The Incorporated Methodologymentioning

confidence: 98%

Section: The Incorporated Methodologymentioning

confidence: 99%

EVO-EXPLORER: A Tool for Designing High-Performance Digital Systems

Sllame

2007

2007 Innovations in Information Technologies (IIT)

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“…Scheduling nodes with higher number of successors reduces variable lifetime [20], i.e. reduces data storage cost.…”

Section: Scheduling Priority Functionmentioning

confidence: 99%

“…However conventional techniques usually address various HLS constraints considering uniform-width resources (same word-length for all components and interconnections) [20][21][22][23][24]. This is mainly due to traditional high-level languages used as high-level synthesis input like the C language which only provides computation types with restricted lengths (typically 8/16/ 32/64 data-widths).…”

Section: High-level Synthesis With Variable Datapathmentioning

confidence: 99%

Word-Length Aware DSP Hardware Design Flow Based on High-Level Synthesis

Gal¹,

Casseau²

2010

J Sign Process Syst

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International audienceMultimedia applications such as video and image processing are often characterized as computation intensive applications. For these applications the word-length of data and instructions is different throughout the application. Generating hardware architectures is not a straightforward task since it requires a deep word-length analysis in order to properly determine what hardware resources are needed. In this paper we suggest an automated design methodology based on high-level synthesis which takes care of data word- length and interconnection resource cost in order to generate area and power efficient fixed-point architectures for DSP applications. Both ASIC and FPGA technologies are targeted. Experimental results show that our proposed approach reduces area by 6% to 42% on FPGA technology and by 9% to 48 % on ASIC compared to previous approaches. Power saving can reach up to 44% on FPGA technology and 36% on ASIC

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“…Approaches such as forcedirected scheduling [12], ELS/ELAS [13], and list scheduling [14] have been proposed. While these approaches can be quite effective for producing results rapidly, these heuristics do not guarantee that the optimal solution will be found.…”

Section: Other Approaches and Heuristicsmentioning

confidence: 99%

A Fast Branch-and-Bound Approach to High-Level Synthesis of Asynchronous Systems

Hansen

Singh

2010

2010 IEEE Symposium on Asynchronous Circuits and Systems

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In this paper, we address the problem of scheduling and allocation for asynchronous systems, and present methods for performing both area-constrained and time-constrained design space exploration. Much of the recent work in this area has been adapted from synchronous approaches, and thereby suffers from the drawback of assuming discrete time (or a discrete approximation). Further, most existing approaches are based on ILP methods, which can suffer from long solution search times for even modest-sized examples.We present instead an approach that does not assume or approximate timing as discrete, and is therefore able to find more optimal solutions for asynchronous systems. The scheduling approach uses a branch-and-bound search strategy with simple, effective heuristics to safely prune the search space, while guaranteeing an optimal solution. In particular, a high-quality initial solution is obtained heuristically, allowing the search space and overall search time to be significantly reduced, particularly when compared to ILP approaches. A 1.9x-180x improvement in run-time is achieved for small examples, and an improvement of multiple orders of magnitude for larger examples (including an example containing over a thousand operations).

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An efficient list-based scheduling algorithm for high-level synthesis

Cited by 26 publications

References 15 publications

EVO-EXPLORER: A Tool for Designing High-Performance Digital Systems

EVO-EXPLORER: A Tool for Designing High-Performance Digital Systems

Word-Length Aware DSP Hardware Design Flow Based on High-Level Synthesis

A Fast Branch-and-Bound Approach to High-Level Synthesis of Asynchronous Systems

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