A Fast Branch-and-Bound Approach to High-Level Synthesis of Asynchronous Systems

Abstract

In this paper, we address the problem of scheduling and allocation for asynchronous systems, and present methods for performing both area-constrained and time-constrained design space exploration. Much of the recent work in this area has been adapted from synchronous approaches, and thereby suffers from the drawback of assuming discrete time (or a discrete approximation). Further, most existing approaches are based on ILP methods, which can suffer from long solution search times for even modest-sized examples.We present instead an approach that does not assume or approximate timing as discrete, and is therefore able to find more optimal solutions for asynchronous systems. The scheduling approach uses a branch-and-bound search strategy with simple, effective heuristics to safely prune the search space, while guaranteeing an optimal solution. In particular, a high-quality initial solution is obtained heuristically, allowing the search space and overall search time to be significantly reduced, particularly when compared to ILP approaches. A 1.9x-180x improvement in run-time is achieved for small examples, and an improvement of multiple orders of magnitude for larger examples (including an example containing over a thousand operations).

Design of asynchronous systems on FPGA using direct mapping and synchronous specification

“…The proposed methodology follows the traditional steps of the behavioral synthesis [12]. The methodology can be divided into four steps:…”

“…For this decomposition style different techniques were proposed to the synthesis of data-paths and controllers [8][9][10][11][12][13][14][15][16]. Recently, there have been several attempts to demonstrate the potential advantages of the asynchronous circuits over its synchronous counterparts [17][18][19][20] and some asynchronous digital systems design methodologies have been developed successfully [5].…”

“…In the first one, the project involves asynchronous data-path, so does not present any delay, but the asynchronous data-path involves dual-rail components, presenting a very high cost [5,11]. In the second variant of "by decomposition" asynchronous circuits design, a delay is inserted in the project with synchronous data-path, defining the cycle time of the transition state [8][9][10][12][13][14][15][16]. The second variant leads to circuits with lower-power consumption, smaller area and simplifies the project when compared with the first variant.…”

Asynchronous Design—Part 2: Systems and Methodologies

“…An optimal asynchronous schedule cannot be obtained from a synchronous formulation merely through a postprocessing step of relaxing the clocking boundaries. 13 Nonetheless, some early asynchronous resource sharing approaches directly adapted the synchronous model, though results were not guaranteed to be optimal.…”

“…3 Others important milestones, using novel architectures, include the counterflow pipeline processor at Sun Microsystems Laboratories, 7 an asynchronous outoforder architecture featuring precise exceptions at University of Utah, 8 a superpipelined multimedia processor at Sharp, 9 the Post Office communication coprocessor at HP Laboratories, 10 and a lowpower sensornetwork processor from Cornell University. 11 Asynchronous design has also been used as a foundation for largescale interprocessor communication, including the Torus routing chip, 12 FLEETzero at Sun Microsystems Laboratories, 13 and the terabitrate commercial crossbar switches of Intel/Fulcrum. 14 Finally, the recent surge of interest in cognitive computing is exemplified by several recent neuromorphic processors IBM's TrueNorth, 15 Stanford University's Neurogrid (Boahen's group), 16 and University of Manchester's SpiNNaker 17 (Furber's group) , all of which use fullyasynchronous interconnection networks to integrate massivelyparallel architectures with thousands (and, eventually, millions) of processing elements.…”