An Efficient Implementation of Boolean Functions and Finite State Machines as Self-Timed Circuits

David, I.; Girrosar, R.; Yoeli, Michael

doi:10.1109/eeis.1989.720129

Cited by 6 publications

(2 citation statements)

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“…'s computation may start even before the preceding computation (with small latency) is finished. To be able to take advantage of such effects we assume that there are acknowledgement mechanisms as presented in [8,16]. Since we consider the (potentially long) wires and the mechanism controlling the I/O of an algorithm as a valuable resource we prefer schemas that use every pin in every step of a time interval.…”

Section: Definition 5 An Algorithm In the -Wired Grid Model Consists Of An Gate Array And A Corresponding -Connection Network In The Confmentioning

confidence: 99%

Efficient Addition on Field Programmable Gate Arrays

Jakoby

Schindelhauer

2001

FST TCS 2001: Foundations of Software Technology and Theoretical Computer Science

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We investigate average efficient adders for grid-based environments related to current Field Programmable Gate Arrays (FPGAs) and VLSI-circuits. Motivated by current trends in FPGA hardware design we introduce a new computational model, called the -wired grid model. The parameter describes the degree of connectivity of the underlying hardware. This model covers among others two-dimensional cellular automata for and VLSI-circuits for . To formalize input and output constraints of such circuits we use the notion of input and output schemas. It turns out that the worst case time and area complexity are highly dependent on the specific choice of I/O schemas. We prove that a set of regular schemas supports efficient algorithms for addition where time and area bounds match lower bounds of a broad class of I/O schemas. We introduce new schemas for average efficient addition on FPGAs and show that addition can be done in expected time for the standard VLSI model and in expected time in the pure grid model. Furthermore, we investigate the rectangular area needed to perform addition with small error probability, called area with high probability. Finally, these results are generalized to the class of prefix functions.

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Section: Definition 5 An Algorithm In the -Wired Grid Model Consists Of An Gate Array And A Corresponding -Connection Network In The Confmentioning

confidence: 99%

Efficient Addition on Field Programmable Gate Arrays

Jakoby

Schindelhauer

2001

FST TCS 2001: Foundations of Software Technology and Theoretical Computer Science

View full text Add to dashboard Cite

show abstract

“…It was fabricated and tested [10], and has thus provided a solid proof of existence. A second asynchronous processor architecture is described in [3], and is based on the design approach presented in [2]. It comprises two parallel components, a data processor and a branch processor.…”

Section: Previous Asynchronous Processor Architecturesmentioning

confidence: 99%