Efficient Addition on Field Programmable Gate Arrays

Jakoby, Andreas; Schindelhauer, Christian

doi:10.1007/3-540-45294-x_19

Cited by 2 publications

(1 citation statement)

References 14 publications

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“…Circuits that work in an asynchronous mode may not get all their input bits at the same time. Similar to [JS01] we therefore make the following definitions. Definition 1.…”

Section: Timing Of a Boolean Circuitmentioning

confidence: 99%

Improving the average delay of sorting

Jakoby¹,

Liśkiewicz²,

Reischuk³

et al. 2009

Theoretical Computer Science

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In previous work we have introduced an average-case measure for the time complexity of Boolean circuits-that is the delay between feeding the input bits into a circuit and the moment when the results are ready at the output gates-and analysed this complexity measure for prefix computations. Here we consider the problem to sort large integers that are given in binary notation. Contrary to a word comparator sorting circuit C where a basic computational element, a comparator, is charged with a single time step to compare two elements, in a bit comparator circuit C a comparison of two binary numbers has to be implemented by a Boolean subcircuit CM called comparator module that is built from Boolean gates of bounded fanin. Thus, compared to C, the depth of C will be larger by a factor up to the depth of CM. Our goal is to minimize the average delay of bit comparator sorting circuits. The worst-case delay can be estimated by the depth of the circuit. For this worst-case measure two topologically quite different designs seems to be appropriate for the comparator modules: a tree-like one if the inputs are long numbers, otherwise a linear array working in a pipelined fashion. Inserting these into a word comparator circuit we get bit level sorting circuits for binary numbers of length m for which the depth is either increased by a multiplicative factor of oder log m or by an additive term of order m. We show that this obvious solution can be improved significantly by constructing efficient sorting and merging circuits for the bit model that only suffer a constant factor time loss on the average if the inputs are uniformly distributed. This is done by designing suitable hybrid architectures of tree compaction and pipelining. These results can also be extended to classes of nonuniform distributions if we put a bound on the complexity of the distributions themselves.

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“…Circuits that work in an asynchronous mode may not get all their input bits at the same time. Similar to [JS01] we therefore make the following definitions. Definition 1.…”

Section: Timing Of a Boolean Circuitmentioning

confidence: 99%

Improving the average delay of sorting

Jakoby¹,

Liśkiewicz²,

Reischuk³

et al. 2009

Theoretical Computer Science

Self Cite

View full text Add to dashboard Cite

show abstract

Improving the Average Delay of Sorting

Jakoby¹,

Liśkiewicz²,

Reischuk³

et al.

Lecture Notes in Computer Science

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Abstract. In previous work we have introduced an average-case measure for the time complexity of Boolean circuits -that is the delay between feeding the input bits into a circuit and the moment when the results are ready at the output gates -and analysed this complexity measure for prefix computations. Here we consider the problem to sort large integers that are given in binary notation. Contrary to a word comparator sorting circuit C where a basic computational element, a comparator, is charged with a single time step to compare two elements, in a bit comparator circuit C a comparison of two binary numbers has to be implemented by a Boolean subcircuit CM called comparator module that is built from Boolean gates of bounded fanin. Thus, compared to C, the depth of C will be larger by a factor up to the depth of CM . Our goal is to minimize the average delay of bit comparator sorting circuits. The worst-case delay can be estimated by the depth of the circuit. For this worst-case measure two topologically quite different designs seems to be appropriate for the comparator modules: a tree-like one if the inputs are long numbers, otherwise a linear array working in a pipelined fashion. Inserting these into a word comparator circuit we get bit level sorting circuits for binary numbers of length m for which the depth is either increased by a multiplicative factor of oder log m or by an additive term of order m . We show that this obvious solution can be improved significantly by constructing efficient sorting and merging circuits for the bit model that only suffer a constant factor time loss on the average if the inputs are uniformly distributed. This is done by designing suitable hybrid architectures of tree compaction and pipelining. These results can also be extended to classes of nonuniform distributions if we put a bound on the complexity of the distributions themselves.

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Efficient Addition on Field Programmable Gate Arrays

Cited by 2 publications

References 14 publications

Improving the average delay of sorting

Improving the average delay of sorting

Improving the Average Delay of Sorting

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