An efficient FIR filter architecture

Evans, Joseph

doi:10.1109/iscas.1993.393799

Cited by 15 publications

(8 citation statements)

References 17 publications

(11 reference statements)

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“…The two rows of full adders map to alternate columns of the chip referred to as 1 and 2 as shown in Figure 4. To reduce congestion, the two shifted versions of the data are distributed among the two sets of full adders, whereas in the previous approach [1], they were routed to the first set of full adders. In the previous tap structure, the sum outputs of the second set of full adders in any tap are fed to the corresponding full adders in the next tap, which are two columns away.…”

Section: Place and Routementioning

confidence: 99%

“…Finite Impulse Response filters without full multipliers and their potential high speed VLSI implementations have received attention over the past decade [1,2,3,4]. An efficient FIR filter architecture suitable for Field Programmable Gate Arrays (FPGA), which requires the coefficients to be a sum or difference of two powerof-two terms was discussed in [1]. In this paper, we present an improved filter tap structure and several mapping techniques which were used to increase the sampling rate.…”

Section: Introductionmentioning

confidence: 99%

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Automatic implementation of FIR filters on field programmable gate arrays

Mohanakrishnan

Evans

1995

IEEE Signal Process. Lett.

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This paper describes a CAD system for automatic implementation of FIR filters on Xilinx Field Programmable Gate Arrays. Given the frequency specifications, this software package designs an FIR filter, optimizes the filter coefficients in the power of two coefficient space and implements it on an FPGA chip. The FPGA specific mapping techniques used to increase speed are discussed. The performance of the typical filters which were implemented is presented.

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Section: Place and Routementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Automatic implementation of FIR filters on field programmable gate arrays

Mohanakrishnan

Evans

1995

IEEE Signal Process. Lett.

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“…For implementing the digital filtering algorithms, the most common approaches are special purpose digital filtering chips and Application-Specific Integrated Circuits (ASICs) for higher rates (Khoo et al, 1993;Laskowski and Samueli, 1992;Evans, 1993) or general purpose digital signal processing chips for audio applications.…”

Section: Introductionmentioning

confidence: 99%

Hardware Approach of a Multipurpose Finite Impulse Response Filter for Real-Time Filtering Applications

Amin

Mamun²,

Rahman

2011

American Journal of Applied Sciences

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Problem statement: Finite Impulse Response (FIR) filters are widely used in various DSP applications. The design of digital FIR filters is a very basic problem in digital signal processing. A FIR filter with multiple operation capability is certainly very useful for any real-time filtering applications. This article presents a multipurpose FIR filter design modeled by the hardware description language VHDL for real-time filtering application. Approach: The VHDL has its concept of concurrency to cope with the parallelism of digital hardware. The novel feature is the capability of the design to accomplish up to 127variable filter order and an arbitrary filter frequency response. The coefficients are calculated by Hamming windowing technique. Basing on selection embedded in the design, the model is able to execute highpass, lowpass, bandstop and bandpass filtering operations. It is set at 8-bit signed data processing. To filter the input data in time domain, Linear Constant Coefficient Difference Equation (LCCDE) is used by the filter. Results: The design outputs are validated through simulation and compilation. The output results are also compared with the MATLAB implemented calculated output results to test the correctness that proves the effectiveness of the design. Conclusion: With the capability of filtering signal in real time mode utilizing arbitrary filter shape, the multipurpose filter proves to be versatile.

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“…As a result the filter remains fixed to a specific transfer function. A number of multiplierless programmable filter architectures have been developed which counter-act this problem [1,2]. Multiplierless FIR filter design techniques such as canonic signed digit (CSD) coefficient encoding [3,4], and primitive operator filter (POF) design [5][6][7] have been shown to produce high performance filters with fast signal processing and reduced area.…”

Section: Introductionmentioning

confidence: 99%

Evolutionary design and adaptation of high performance digital filters within an embedded reconfigurable fault tolerant hardware platform

Hounsell

Arslan

Thomson

2004

Soft Computing - A Fusion of Foundations, Methodologies and App

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Finite impulse response filters (FIRs) are crucial devices for robust data communication and manipulation. Multiplierless filters have been shown to produce high performance systems with fast signal processing and reduced area. Furthermore, the distributed architecture inherent in multiplierless filters makes it a suitable candidate for fault tolerant design. Alternative approaches to the design of fault tolerant systems have been proposed using evolutionary algorithms (EAs) and the concept of evolvable hardware (EHW). This paper presents an evolvable hardware platform for the automated design and adaptation of multiplierless digital filters. Filters are realised within a dedicated programmable logic array (PLA) based on the Primitive Operator Filter design principle. The platform employs a genetic algorithm to autonomously configure the PLA for a given set of coefficients. The ability of the platform to adapt to increasing numbers of faults was investigated through the ''evolution'' of a 31-tap lowpass FIR filter. Results show that the functionality of filters evolved on the PLA was maintained despite an increasing number of faults covering up to 25% of the PLA area. Additionally, three PLA initialisation methods were investigated to ascertain which produced the fastest fault recovery times. It was shown that seeding a population of random configuration-strings with the best configuration currently obtained resulted in a 6 fold increase in fault recovery speed over other methods investigated.

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An efficient FIR filter architecture

Cited by 15 publications

References 17 publications

Automatic implementation of FIR filters on field programmable gate arrays

Automatic implementation of FIR filters on field programmable gate arrays

Hardware Approach of a Multipurpose Finite Impulse Response Filter for Real-Time Filtering Applications

Evolutionary design and adaptation of high performance digital filters within an embedded reconfigurable fault tolerant hardware platform

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