Evolutionary design and adaptation of high performance digital filters within an embedded reconfigurable fault tolerant hardware platform

Abstract

Finite impulse response filters (FIRs) are crucial devices for robust data communication and manipulation. Multiplierless filters have been shown to produce high performance systems with fast signal processing and reduced area. Furthermore, the distributed architecture inherent in multiplierless filters makes it a suitable candidate for fault tolerant design. Alternative approaches to the design of fault tolerant systems have been proposed using evolutionary algorithms (EAs) and the concept of evolvable hardware (EHW). This paper presents an evolvable hardware platform for the automated design and adaptation of multiplierless digital filters. Filters are realised within a dedicated programmable logic array (PLA) based on the Primitive Operator Filter design principle. The platform employs a genetic algorithm to autonomously configure the PLA for a given set of coefficients. The ability of the platform to adapt to increasing numbers of faults was investigated through the ''evolution'' of a 31-tap lowpass FIR filter. Results show that the functionality of filters evolved on the PLA was maintained despite an increasing number of faults covering up to 25% of the PLA area. Additionally, three PLA initialisation methods were investigated to ascertain which produced the fastest fault recovery times. It was shown that seeding a population of random configuration-strings with the best configuration currently obtained resulted in a 6 fold increase in fault recovery speed over other methods investigated.

Evolvable Hardware

“…In particular, structures of multiplierless filters were sought by many authors (Wade et al 1994;Hounsell et al 2004;Erba et al 2001;Gwaltney and Dutton 2005). Regardless of filter representation, the fitness function is usually constructed in the frequency domain.…”

Evolutionary Design of Digital Circuits: Where Are Current Limits?

“…Evolvable hardware was applied to high-performance and adaptive systems in which the problem specification is unknown beforehand and can vary in time [6,23,20,8]. Its main objective is the development of a new generation of hardware, self-configurable and evolvable, environment-aware, which can adaptively reconfigure to achieve optimal signal processing, survive and recover from faults and degradation, and improve its performance over lifetime of operation [23].…”

“…An important property of this approach is that the size of chromosome remains similar to CGP while the complexity of circuits can grow arbitrarily. Functionallevel evolution was applied to many real-world problems, for example, to the design of multiplier-less filters [8], image filters [15], multipliers [1] etc. In order to illustrate the method, this section describes evolution of image filters and benchmark circuits.…”

Runtime Bitstream Relocation based Intrinsic Evolvable System

“…Owing to no commercial evolvable platform available, much research work has been undertaken on evolvable platform since the birth of EHW. The earliest evolvable platform includes generic array logic (GAL) [9] and programmable logic array (PLA) [10], due to the limited logic resource of these two simple programmable logic devices (PLD), only relatively simple circuit could be evolved. The Xilinx XC6200 series field programmable gate array (FPGA), with the feature of known bitstream format and safe configuration, has made great promotion in intrinsic EHW.…”