An efficient fault-tolerant routing algorithm in NoCs to tolerate permanent faults

Akbar, Reza; Etedalpour, Ali Asghar; Safaei, Farshad

doi:10.1007/s11227-016-1749-0

Cited by 13 publications

(4 citation statements)

References 38 publications

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“…These algorithms add some virtual or physical channels to attain deadlock-free communication [13,14]. Various fault-tolerant routing algorithms have been proposed [15]. A partially adaptive fault-tolerant routing algorithm built on a negative-first approach is proposed in Glass and Ni [16].…”

Section: Related Researchmentioning

confidence: 99%

A Network Adaptive Fault-Tolerant Routing Algorithm for Demanding Latency and Throughput Applications of Network-on-a-Chip Designs

et al. 2020

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Scalability is a significant issue in system-on-a-chip architectures because of the rapid increase in numerous on-chip resources. Moreover, hybrid processing elements demand diverse communication requirements, which system-on-a-chip architectures are unable to handle gracefully. Network-on-a-chip architectures have been proposed to address the scalability, contention, reusability, and congestion-related problems of current system-on-a-chip architectures. The reliability appears to be a challenging aspect of network-on-a-chip architectures because of the physical faults introduced in post-manufacturing processes. Therefore, to overcome such failures in network-on-a-chip architectures, fault-tolerant routing is critical. In this article, a network adaptive fault-tolerant routing algorithm is proposed, where the proposed algorithm enhances an efficient dynamic and adaptive routing algorithm. The proposed algorithm avoids livelocks because of its ability to select an alternate outport. It also manages to bypass congested regions of the network and balances the traffic load between outports that have an equal number of hop counts to its destination. Simulation results verified that in a fault-free scenario, the proposed solution outperformed a fault-tolerant XY by achieving a lower latency. At the same time, it attained a higher flit delivery ratio compared to the efficient dynamic and adaptive routing algorithm. Meanwhile, in the situation of a faulty network, the proposed algorithm could reach a higher flit delivery ratio of up to 18% while still consuming less power compared to the efficient dynamic and adaptive routing algorithm.

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Section: Related Researchmentioning

confidence: 99%

A Network Adaptive Fault-Tolerant Routing Algorithm for Demanding Latency and Throughput Applications of Network-on-a-Chip Designs

et al. 2020

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“…Any routing method should aim to transport packets to their destinations, distribute network traffic so as to minimize packet interference, choose a short route, reduce packet delays, and ultimately improve network performance. The routing algorithms have a major significance in NoCs as it plays crucial role on the performance, complexity and implementation cost of NoC [4], [5]. There can be broadly classified depending upon the routing decisions made into deterministic routing, in which data packets take fixed pathway towards destination based on designated standards and adaptive routing, in which the pathway depends on the network conditions.…”

Section: Introductionmentioning

confidence: 99%

Design of fault tolerant algorithm for network on chip router using field programmable gate array

Shahane,

Kurup

2024

IJRES

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Many internet protocol (IP) modules are present in contemporary system on chips (SoCs). This could provide an issue with interconnection among different IP modules, which would limit the system's ability to scale. Traditional bus-based SoC architectures have a connectivity bottleneck, and network on chip (NoC) has evolved as an embedded switching network to address this issue. The interconnections between various cores or IP modules on a chip have a significant impact on communication and chip performance in terms of power, area latency and throughput. Also, designing a reliable fault tolerant NoC became a significant concern. In fault tolerant NoC it becomes critical to identify faulty node and dynamically reroute the packets keeping minimum latency. This study provides an insight into a domain of NoC, with intention of understanding fault tolerant approach based on the XY routing algorithm for 4×4 mesh architecture. The fault tolerant NoC design is synthesized on Field programmable gate array (FPGA).

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“…Many faults must be tolerated to sustain chip production yield and reliable operation [18]. Meanwhile, this emphasis on permanent NoC faults significantly influences routine [19].…”

Section: Introductionmentioning

confidence: 99%

Design analysis of moth-flame optimized fault tolerant technique for minimally buffered network-on-chip router

Sumithra,

Lakshminarayanan Venkatara,

Suresh Kumar

et al. 2024

IJEECS

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A network on a chip is a solitary silicon chip utilized to perform the communication characteristics of large-scale (LSI) to very large-scale integration (VLSI) systems. Network-on-chip (NoC) architecture includes links, network interfaces (NI), and routers to unite with external memories or processors. NoC is designed to flow messages from the source module to the destination module through several links involving routing decisions. The design of NoC is complex and the buffer section’s expensiveness creates problems while providing secured data service. Moreover, routers and links in NoC setups are liable to faults. This work introduces a minimal buffered router, and the faults in the network are optimized using moth flame optimized (MFO) fault-tolerant technique. The software named Xilinx ISE design suite 14.5 is employed for the minimum buffered router model. The suggested scheme is operated with less area, low power (0.241 mW), and high speed (965.261 Megahertz (MHz)) when matched with previous works.

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An efficient fault-tolerant routing algorithm in NoCs to tolerate permanent faults

Cited by 13 publications

References 38 publications

A Network Adaptive Fault-Tolerant Routing Algorithm for Demanding Latency and Throughput Applications of Network-on-a-Chip Designs

A Network Adaptive Fault-Tolerant Routing Algorithm for Demanding Latency and Throughput Applications of Network-on-a-Chip Designs

Design of fault tolerant algorithm for network on chip router using field programmable gate array

Design analysis of moth-flame optimized fault tolerant technique for minimally buffered network-on-chip router

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