Design analysis of moth-flame optimized fault tolerant technique for minimally buffered network-on-chip router
Subramanian Sumithra,
Nagaiyanallur Lakshminarayanan Venkatara,
Subramani Suresh Kumar
et al.
Abstract:<span>A network on a chip is a solitary silicon chip utilized to perform the communication characteristics of large-scale (LSI) to very large-scale integration (VLSI) systems. Network-on-chip (NoC) architecture includes links, network interfaces (NI), and routers to unite with external memories or processors. NoC is designed to flow messages from the source module to the destination module through several links involving routing decisions. <br /> The design of NoC is complex and the buffer section’… Show more
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