An Efficient Diagnosis Pattern Generation Procedure to Distinguish Stuck-at Faults and Bridging Faults

Abstract

Fault Diagnosis is a critical process to identify the locations of physical defects in advanced integrated circuits. Current diagnosis tools often report multiple types of faults as defect candidates. Thus an efficient method to distinguish different types of faults is highly desired. Stuck-at and bridging faults are two most commonly used DC fault models during diagnosis. In this paper we present an efficient diagnosis pattern generation procedure to distinguish stuck-at faults and bridging faults. Two major techniques are proposed. The first one is a fault-inactivation methodFIM) that can quickly distinguish most fault pairs by inactivating one fault while detecting the other in each fault pair. The second one is a fault-types-transformation method (FTTM) that can transform the problem of distinguishing a stuck-at fault and a bridging fault into the problem of detecting a stuck-at fault. Both methods involve only one copy of the original circuit and require only an ordinary ATPG tool for stuck-at faults. Furthermore, both methods can deal with multiple fault pairs at a time and thus not only is the required CPU time small but also the dynamic test compaction capability of the ATPG tool can be utilized. Experiments on a large number of randomly selected fault pairs in ISCAS'89 and IWLS'05 benchmark circuits have been carried out. The results show that the FIM can distinguish about 91.9% of distinguishable fault pairs quickly and the FTTM can distinguish all other distinguishable fault pairs and identify all equivalent fault pairs. The average ratio of the number of diagnosis patterns over that of the test patterns for stuck-at faults is only 0.64. On average, one diagnosis pattern can distinguish 10.89 fault pairs.

An effective way to generate the shift timing constraints and sanity checks

“…This testing will happen in three phases first load, second shift then capture [8], as each phase depends on the clock edge, clock cycles play a significant role in the timing. In the shift to test the functionality, mainly against any stuck-at faults [9], [10] of the designed chip, the sequential devices will be stitched in the chain order, and the test pattern to detect the fault is applied in the series.…”