An efficient algorithm for sequential circuit test generation

Kelsey, T.P.; Saluja, Kewal K.; Lee, S.Y.

doi:10.1109/12.247839

Cited by 87 publications

(20 citation statements)

References 15 publications

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“…The results for test sequences generated by HITEC [13] and FASTEST [14] are shown in Tables 5 and 6, respectively. Original test sequences were generated for Table 5.…”

Section: Resultsmentioning

confidence: 99%

Static test compaction for IDDQ testing of bridging faults in sequential circuits

et al. 2000

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This paper presents a static test compaction method for IDDQ testing of sequential circuits. Test compaction reduces test application time and tester memory and consequently reduces testing cost. Particularly for IDDQ testing, measurement of IDDQ is time-consuming, and thus test compaction is a very important issue. In the proposed method, test subsequences are removed and replaced with shorter subsequences by considering state transition of a circuit under test, so that original fault coverage is guaranteed. The effectiveness of the proposed method is demonstrated by experimental results for ISCAS89 benchmark circuits. © 2000 Scripta Technica, Syst Comp Jpn, 31(11): 4150, 2000

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“…The results for test sequences generated by HITEC [13] and FASTEST [14] are shown in Tables 5 and 6, respectively. Original test sequences were generated for Table 5.…”

Section: Resultsmentioning

confidence: 99%

Static test compaction for IDDQ testing of bridging faults in sequential circuits

et al. 2000

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“…To be fair, we report the total ATPG time, which includes time required for reading netlists, design rule checking, learning, test generation, and fault simulation. Although not reported here when several sequential ATPG programs, such as GENTEST [6], HITEC [29], and FASTEST [20], were used on both acyclic sequential circuits and C-ATPG circuits, our new combinational method produced equal or better coverages with an average 40% less CPU time [21] despite the increased PIs and gates in the C-ATPG circuits.…”

Section: Resultsmentioning

confidence: 99%

Combinational automatic test pattern generation for acyclic sequential circuits

Kim

Agrawal

Saluja

2005

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-It is known that the complexity of automatic test pattern generation (ATPG) for acyclic sequential circuits is similar to that of combinational ATPG. The general problem, however, requires time-frame expansion and multiple-fault detection and hence does not allow the use of available combinational ATPG programs. The first contribution of this work is a combinational single-fault ATPG method for the most general class of acyclic sequential circuits. Without inserting any real hardware, we create a functionally equivalent "balanced" ATPG model of the circuit in which all reconverging paths have the same sequential depth. Some primary inputs and gates are duplicated in this model, which is converted into a combinational circuit by shorting all flip-flops. A test vector obtained by a combinational ATPG program for a fault in this combinational circuit is transformed into a test sequence to detect a corresponding fault in the original sequential circuit. A combinational ATPG program finds tests for all but a small set of faults that must be explicitly detected as multiple-faults. Those are modeled for ATPG using the second contribution of this work, which is a generalized method to model any given multiple stuck-at fault as a single stuck-at fault. The procedure requires insertion of at most + 3 modeling gates for a fault of multiplicity . We show that the modeled circuit is functionally equivalent to the original circuit and the targeted multiple fault is equivalent to the modeled single stuck-at fault. Benchmark results show at least an order of magnitude saving in the ATPG CPU time by the new combinational method over sequential ATPG.Index Terms-Acyclic sequential circuit, automatic test pattern generation (ATPG), balanced model, combinational test generation, design for test (DFT), partial scan, test.

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“…Each strategy has advantages and drawbacks, and are separately discussed in [Kel93]. In MOSAIC, we choose to switch between two of them: Forward Reverse time processing and Forward Only time processing.…”

Section: / Sequential Techniquementioning

confidence: 99%

“…During the past decade much academic work has been done in an attempt to solve the problem of Automatic Test Pattern Generation (ATPG) for sequential circuits [Mar86,Che88a,Che88b,MaD88,Gou91,Lee91,Nie91,Ono91,Kel93]. More recently several industrial tools (HITEC, GENTEST, ...) have been developed for inclusion in CAD suites.…”

Section: / Introductionmentioning

confidence: 99%

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MOSAIC: a multiple-strategy oriented sequential ATPG for integrated circuits

Dargelas¹,

Gauthron²,

Bertrand³

Proceedings European Design and Test Conference. ED &Amp; TC 97

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The paper proposes a novel approach in an attempt to solve the test problem for sequential circuits. Up until I / IntroductionDuring the past decade much academic work has been done in an attempt to solve the problem of Automatic Test Pattern Generation (ATPG) for sequential circuits [Mar86,Che88a,Che88b,MaD88,Gou91,Lee91,Nie91,Ono91,Kel93]. More recently several industrial tools (HITEC, GENTEST, ...) have been developed for inclusion in CAD suites. Two main techniques are classically used to generate test vectors for circuits, namely, the deterministic approach and the simulation-based approach. The simulation-based approach may use either random or genetic [Saa94, Pri94, Rud95] generation. In some cases both techniques are found to be combined in the same tool, in others they are separated.It seems that no single technique gives the best results for all the test cases. Taking this fact into account, we decided to develop a new Sequential-ATPG, the so-called MOSAIC tool, which aims at being able to cope with industrial circuits. The designs targeted are real designs, which may or may not be provided with partial scan. This means that some sequential elements are not included in scan chains. In addition to this, depending on the circuit under consideration, the sequential elements (FFs) may or may not be provided with reset facilities. Normally, an initialization sequence is given by the designer to set the circuit into its reset state, but there are some exceptions that we have to deal with. As a consequence we do not assume a reset state for these sequential elements.The fundamental concepts on which our approach is based originates mainly from the basic works of Fujiwara and Shimono [Fuj83] on the FAN algorithm and Gouder and Kaibel [Gou91] on the CONSEQUENT model. Different strategies we have used are derived from various papers : [Che88a, Sch88, Sch89, Nie91, Lee91, Ono91, Kel93]. Section II describes the techniques commonly used in test generation and explains the way we have modified these techniques in MOSAIC. Section III exposes our implementation of the Multiple Strategy technique derived from [Min89], and Section IV describes our approach for sequential circuits. Section V discusses Strategy choices, then, Section VI presents the MOSAIC results obtained on ISCAS89 benchmark circuits. Lastly, Section VII gives conclusions and proposes some future extensions. II / Basic TechniquesThe various techniques presented in this section are not limited to combinational circuits. They are used with the iterative array representation of sequ. circuits [Abr90]. II.1 / Value system

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An efficient algorithm for sequential circuit test generation

Cited by 87 publications

References 15 publications

Static test compaction for IDDQ testing of bridging faults in sequential circuits

Static test compaction for IDDQ testing of bridging faults in sequential circuits

Combinational automatic test pattern generation for acyclic sequential circuits

MOSAIC: a multiple-strategy oriented sequential ATPG for integrated circuits

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