An automatic technique for optimizing Reed-Solomon codes to improve fault tolerance in memories

Abstract

IEEE Design & Test of ComputersTHE TECHNOLOGICAL EVOLUTION of the IC fabrication process, consisting of device shrinking, power supply reduction, and increasing operating speeds, has significantly reduced the manufacturing yield and reliability of very deep-submicron (VDSM) ICs when various noise sources are present, as recent roadmaps (the International Technology Roadmap for Semiconductors, Medea, and IEEE Design & Test) have demonstrated. As a result, more and more applications must be robust in the presence of multiple faults. Consequently, fault tolerance in storage devices such as high-density and highspeed memories operating at low voltage, is a main concern nowadays and thus the focus of this work.Faults can occur during the fabrication process, with direct consequences in terms of yield and memory operation. Using VDSM technologies increases the chances of manufacturing defects. It is important to design fault-tolerant mechanisms to ensure that a memory operates correctly, even in the presence of defects such as open and short gates and connections that can result in stuck-at faults or coupling faults in memory cells.

Resilient computer system design

“…12 The RS decoding process has several stages to get the location of the error and correct it. Implementations of RS codes can be found in (Neuberger et al 2005;.…”

Design and analysis of efficient synthesis algorithms for EDAC functions in FPGAs

“…There is another work [37] whose main aim is to obtain small and fast implementations of RS codes in FPGAs by choosing the most suitable generator polynomials and multiplication constants. In that work, the optimized RS codes are intended to be used in combination with SEC-DED Hamming codes for protecting memories from SEU, but the optimization of the latter part is not considered.…”

Extend orthogonal Latin square codes for 32-bit data protection in memory applications

“…A different option is to adopt more advanced ECCs that can deal with more than one error, such as Bose-Chaudhuri-hocquenghem (BCH) codes [14], and Reed-Solomon (RS) codes [15]. Due to the complexity of decoding algorithms, codes with strong correction capabilities cost more overhead in terms of delay and power, which can limit their applicability in memory designs [16].…”