This paper discusses fault-tolerant techniques for SRAM-based FPGAs. These techniques can be based on circuit level modifications, with obvious modifications in the programmable architecture, or they can be implemented at the high-level description, without modification in the FPGA architecture. The high-level method presented in this work is based on Triple Modular Redundancy (TMR) and a combination of Duplication Modular Redundancy (DMR) with Concurrent Error Detection (CED) techniques, which are able to cope with upsets in the combinational and in the sequential logic. The methodology was validated by fault injection experiments in an emulation board. Results have been analyzed in terms of reliability, input and output pin count, area and power dissipation.
Universidade Federal do Rio Grande do Sul (UFRGS) FERNANDA DE LIMA Universidade Estadual do Rio Grande do Sul (UERGS) and LUIGI CARRO and RICARDO REIS Universidade Federal do Rio Grande do Sul (UFRGS)SRAMs are used nowadays in almost every electronic product. However, as technology shrinks transistor sizes, single and multiple bit upsets only observable in space applications previously are now reported at ground level. This article presents a high level technique to protect SRAM memories against multiple upsets based on correcting codes. The proposed technique combines Reed Solomon code and Hamming code to assure reliability in presence of multiple bit flips with reduced area and performance penalties. Multiple upsets were randomly injected in various combinations of memory cells to evaluate the robustness of the method. The experiment was emulated in a Virtex FPGA platform. Results show that 100% of the injected double faults and a large amount of multiple faults were corrected by the method.
IEEE Design & Test of ComputersTHE TECHNOLOGICAL EVOLUTION of the IC fabrication process, consisting of device shrinking, power supply reduction, and increasing operating speeds, has significantly reduced the manufacturing yield and reliability of very deep-submicron (VDSM) ICs when various noise sources are present, as recent roadmaps (the International Technology Roadmap for Semiconductors, Medea, and IEEE Design & Test) have demonstrated. As a result, more and more applications must be robust in the presence of multiple faults. Consequently, fault tolerance in storage devices such as high-density and highspeed memories operating at low voltage, is a main concern nowadays and thus the focus of this work.Faults can occur during the fabrication process, with direct consequences in terms of yield and memory operation. Using VDSM technologies increases the chances of manufacturing defects. It is important to design fault-tolerant mechanisms to ensure that a memory operates correctly, even in the presence of defects such as open and short gates and connections that can result in stuck-at faults or coupling faults in memory cells.
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