An automated wafermap fast test for bipolar induced breakdown in NMOS transistors

Gaston, G.J.; Bold, B.S.; Mason, Jerod

doi:10.1109/icmts.1994.303508

Cited by 4 publications

(3 citation statements)

References 8 publications

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“…I conclude that the increase of avalanche breakdown voltage and the increase of exponential slope of the avalanche multiplication factor with temperature compensate the increase in bipolar gain with temperature. By measurement, parameter extraction and simulation the postulation of Gaston [12] has been proven, even up to 300°C. If the extracted parameters describing snap back would be specified in process documents, circuit designers could use them to identify and solve problems related to both ESD protection circuits and EOS.…”

Section: Resultsmentioning

confidence: 98%

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Characterization of snap-back breakdown and its temperature dependence up to 300°C including circuit-level model and simulation

Uffmann

1998

SPIE Proceedings

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The MOS snap-back phenomenon and its temperature dependence were investigated up to 300°C by measurement, parameter extraction and simulation using silicided LDD-NMO •ransistors. The snap-back sustaining voltage increases from 8.25V at room temperature to 8.9V at 300°C r LeO.56tffl). By using extracted parameters for a simple lumped element model I explain this behaviour originating from an increasing avalanche breakdown voltage and increasing exponential slope of avalanche multiplication factor compensating the increase in bipolar gain with temperature. The simulation of N-curves on circuit level using PSPICE shows an acceptable matching to the measured IV-curves. If the extracted parameters describing snap back would be specified in process documents, circuit designers could use them to identify and solve problems related to both ESD protection circuits and EOS. The results are also relevant for high temperature operation of electronics, which is a performance issue ofgrowing importance.

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Section: Resultsmentioning

confidence: 98%

“…Gaston et a!. [12] investigated the temperature sensitivity of snap-back in the range from 25°C to 150°C. They found no significant change of snap-back sustaining voltage with temperature and postulated a compensation of the different temperature effects.…”

Section: Introductionmentioning

confidence: 99%

Characterization of snap-back breakdown and its temperature dependence up to 300°C including circuit-level model and simulation

Uffmann

1998

SPIE Proceedings

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“…The snap-back behavior has been widely studied since the early works by Troutman [9], Toyabe et al [10] and Sun et al [1 1] on one hand as a parasitic effect leading to failure of output transistors in the event of ESD [12], [8], on the other hand as a usefiul mechanism in ESD input protection circuits [13], [14]. Gaston et al [15] investigated the temperature sensitivity of snap-back in the range from 25°C to 125°C. They found no significant change of snap-back breakdown voltage with temperature, but did not specify for which of the considered processes (O.5im, O.7tm, 1 .Oim and 1 .4gm) the temperature dependence was evaluated.…”

Section: Introductionmentioning

confidence: 99%

Snap-back temperature dependence for an Epi-CMOS ASIC-process up to 250 degrees C

et al. 1996

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Due to economical reasons junction isolated CMOS should be extensively exploited for temperature resistant electronics. A limitation at high temperatures is given by parasitic effects in the substrate, namely leakage currents, latch-up, and snap-back. Snap-back is caused by the parasitic bipolar action of single MOS transistor structures. We have investigated the temperature dependence of the snap-back phenomenon up to 250°C using silicided LDD-MOS transistors with gate lengths of O.8tm and 1 .Ojtm as test devices. Measurements were performed dynamically with short pulses of rectangular shape. The snap-back breakdown voltage of O.8jim NMOS transistors decreases from 14.3V at room temperature to 1 O.6V at 250°C and the triggering voltage for second breakdown from approximately 9.4V at RT to 6.2V at 250°C. For PMOS transistors no snap-back was observed up to 20V pulse height. The results show that snap-back is not a problem for this CMOS process up to the specified power supply voltage of 5V. To consider shrinking effects we performed 2-dim FEM simulations. At high temperatures, the breakdown voltage is reduced with increasing temperature and decreasing gate length. This correlates to a value of the current gain of the parasitic bipolar transistor 3>l at the breakdown point. The commonly applied measures for designing processes with shorter gate lengths, like e.g. higher tub doping, are also sufficient to avoid snap-back under usual bias conditions even at temperatures up to 250°C.

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Impact of scaling on the high current behavior of RF CMOS technology

Boselli

Reddy

Duvvury

2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual.

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An automated wafermap fast test for bipolar induced breakdown in NMOS transistors

Cited by 4 publications

References 8 publications

Characterization of snap-back breakdown and its temperature dependence up to 300°C including circuit-level model and simulation

Characterization of snap-back breakdown and its temperature dependence up to 300°C including circuit-level model and simulation

Snap-back temperature dependence for an Epi-CMOS ASIC-process up to 250 degrees C

Impact of scaling on the high current behavior of RF CMOS technology

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