TECHNOLOGIES INVESTIGATEDIn this study, through a detailed analysis of the last four CMOS technology nodes targeting similar applications, the intrinsic latch-up process sensitivity will be investigated in an attempt to assess in which measure latch-up will continue to be a major reliability concern for future CMOS technologies. [Keywor-dy: Latch-up, CMOS for low-power applications, CMOS Scaling, High current behavior] Latch-up (LU) in CMOS technologies is a well-established 0-7803-8803-8/05/~20.