Snap-back temperature dependence for an Epi-CMOS ASIC-process up to 250 degrees C

Abstract

Due to economical reasons junction isolated CMOS should be extensively exploited for temperature resistant electronics. A limitation at high temperatures is given by parasitic effects in the substrate, namely leakage currents, latch-up, and snap-back. Snap-back is caused by the parasitic bipolar action of single MOS transistor structures. We have investigated the temperature dependence of the snap-back phenomenon up to 250°C using silicided LDD-MOS transistors with gate lengths of O.8tm and 1 .Ojtm as test devices. Measurements were performed dynamically with short pulses of rectangular shape. The snap-back breakdown voltage of O.8jim NMOS transistors decreases from 14.3V at room temperature to 1 O.6V at 250°C and the triggering voltage for second breakdown from approximately 9.4V at RT to 6.2V at 250°C. For PMOS transistors no snap-back was observed up to 20V pulse height. The results show that snap-back is not a problem for this CMOS process up to the specified power supply voltage of 5V. To consider shrinking effects we performed 2-dim FEM simulations. At high temperatures, the breakdown voltage is reduced with increasing temperature and decreasing gate length. This correlates to a value of the current gain of the parasitic bipolar transistor 3>l at the breakdown point. The commonly applied measures for designing processes with shorter gate lengths, like e.g. higher tub doping, are also sufficient to avoid snap-back under usual bias conditions even at temperatures up to 250°C.