An Assessment of the Location of As-Grown Electron Traps in$hboxHfO_2$/HfSiO Stacks

Zhang, J.F.; Zhao, Ce Zhou; Zahid, Mohammed; Groeseneken, G.; Degraeve, R.; Gendt, Stefan De

doi:10.1109/led.2006.882566

Cited by 41 publications

(26 citation statements)

References 12 publications

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“…This new class of gate dielectrics requires new measurement methods and analysis. In particular, hafnium (Hf)-based oxides, which are being widely accepted as a leading candidate for high-κ gate dielectrics [1], exhibits high density of as-grown structural defects [2][3][4][5][6][7][8][9][10][11][12][13][14][15][16], some representing electron traps that complicate the evaluation of "intrinsic" performance in high-k gate stacks.…”

Section: Introductionmentioning

confidence: 99%

The Pulsed I_d-V_gmethodology and Its Application to the Electron Trapping Characterization of High-κ gate Dielectrics

Young¹,

Heh

Choi

et al. 2010

JSTS:Journal of Semiconductor Technology and Science

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Section: Introductionmentioning

confidence: 99%

The Pulsed I_d-V_gmethodology and Its Application to the Electron Trapping Characterization of High-κ gate Dielectrics

Young¹,

Heh

Choi

et al. 2010

JSTS:Journal of Semiconductor Technology and Science

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“…They similarly behave, i.e., a ΔV TH over half voltage, which is dominated by as-grown defects, and highly dynamic trapping and detrapping with the energy level above the bottom edge of the Si conduction band [9]- [11], [13], [15], [21], [26], [27]. There are differences, however, in their CCS.…”

Section: Resultsmentioning

confidence: 99%

“…Fig. 4 shows that the threshold voltage can be shifted by over half a volt when V GTRAP = 2.0 V was applied for only 100 μs, which is equivalent to an effective charge density of 1.6 × 10 13 cm −2 [21]. A further examination of the kinetic behavior of ΔV TH shows that it can be broadly divided into two regions: a rapidly rising initial period for trapping time less than 100 μs, which is followed by a small and gradual increase.…”

Section: Resultsmentioning

confidence: 99%

“…A further examination of the kinetic behavior of ΔV TH shows that it can be broadly divided into two regions: a rapidly rising initial period for trapping time less than 100 μs, which is followed by a small and gradual increase. On one hand, the rapid initial trapping indicates that there are as- grown electron traps and they dominate the trapping [9]- [11], [13], [15], [21]. On the other hand, the gradual and linear rise against logarithmic time is a signature of new trap generation [22]- [24].…”

Section: Resultsmentioning

confidence: 99%

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Characterization of Electron Traps in Si-Capped Ge MOSFETs With $\hbox{HfO}_{2}/\hbox{SiO}_{2}$ Gate Stack

Benbakhti

Zhang

et al. 2012

IEEE Electron Device Lett.

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Si-capped Ge MOSFETs have good compatibility with existing processes, and promising results have been reported. The process is becoming sufficiently mature to warrant assessment of device reliability. Good time-dependent dielectric breakdown performance has been observed, and negative-biastemperature-instability susceptibility is better than Si counterparts. Electron trapping is shown to be problematic and affects devices through positive bias temperature instability and hot carrier injection. This letter characterizes electron trapping in HfO 2 /SiO 2 stacks on Si-capped Ge. Trapping is substantial, increasing with V G and reaching ∼10 13 cm −2 in 100 μs under V G = 2.0 V. We report, for the first time, two distinctive capture cross sections (CCS) by measuring the transient gate current. The large CCS can be ∼10 −12 cm 2 and reduces for a higher oxide field, which is a signature of coulombic attractive centers. The small CCS is on the order of 10 −14 cm 2 , which is a typical value found for electron traps in SiO 2 and HfO 2 /SiO 2 stacks on Si.Index Terms-Electron traps, Ge MOSFETs, HfO 2 , hot carriers, negative bias temperature instability (NBTI), negative charges, positive bias temperature instability (PBTI), reliability, Si capping.

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“…15a shows that this assumption does not agree with the test data. Another popular assumption is that the as-grown traps are 'uniformly' distributed within the Hf-layer, like the generated traps in SiO 2 (22). When this assumption is used to fit the test data, Fig.…”

Section: Trapping Kinetics and Capture Cross Sectionsmentioning

confidence: 99%

Instability and Defects in Gate Dielectric: Similarity and Differences Between Hf-Stacks and SiO2

et al. 2007

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To control gate leakage current, Hf-based dielectrics have been selected for replacing SiON. Hf-stacks generally suffer from more defects than SiO2. This work reviews the latest progress in the understanding of these defects and compares them with those in SiO2. Attention will be focused on the stress-induced negative charging and the process-induced positive charging. On the negative charging, difficulties for characterizing the highly unstable trapping in thin Hf-layers will be tackled. Key trap properties are determined, including capture cross sections, effective density and spatial location. It is found that the capture cross section of as-grown electron traps in Hf-stacks is similar to that of generated electron traps in SiO2. On process-induced positive charges, it will be shown that Hf-stacks and SiO2 also have common features, including a large sample-to-sample variation, mobile and fixed charges, and stability. Overall, Hf-stacks, especially nitrided, behave like an inferior or stressed SiO2.

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An Assessment of the Location of As-Grown Electron Traps in$hboxHfO_2$/HfSiO Stacks

Cited by 41 publications

References 12 publications

The Pulsed I_d-V_gmethodology and Its Application to the Electron Trapping Characterization of High-κ gate Dielectrics

The Pulsed I_d-V_gmethodology and Its Application to the Electron Trapping Characterization of High-κ gate Dielectrics

Characterization of Electron Traps in Si-Capped Ge MOSFETs With $\hbox{HfO}_{2}/\hbox{SiO}_{2}$ Gate Stack

Instability and Defects in Gate Dielectric: Similarity and Differences Between Hf-Stacks and SiO2

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An Assessment of the Location of As-Grown Electron Traps in$hboxHfO_2$/HfSiO Stacks

Cited by 41 publications

References 12 publications

The Pulsed Id-Vgmethodology and Its Application to the Electron Trapping Characterization of High-κ gate Dielectrics

The Pulsed Id-Vgmethodology and Its Application to the Electron Trapping Characterization of High-κ gate Dielectrics

Characterization of Electron Traps in Si-Capped Ge MOSFETs With $\hbox{HfO}_{2}/\hbox{SiO}_{2}$ Gate Stack

Instability and Defects in Gate Dielectric: Similarity and Differences Between Hf-Stacks and SiO2

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The Pulsed I_d-V_gmethodology and Its Application to the Electron Trapping Characterization of High-κ gate Dielectrics

The Pulsed I_d-V_gmethodology and Its Application to the Electron Trapping Characterization of High-κ gate Dielectrics