An approximation algorithm for fully testable kEP-SOP networks

Abstract

Multi-level logic synthesis yields much more compact expressions of a given Boolean function with respect to standard two-level sum of products (SOP) forms. On the other hand, minimizing an expression with more than two-levels can take a large time. In this paper we introduce a novel algebraic four-level expression, named k-EXOR-projected sum of products (kEP-SOP) form, whose synthesis can be performed in polynomial time with an approximation algorithm starting from a minimal SOP. Our experiments show that the resulting networks can be obtained in very short computational time and often exhibit a high quality. We also study the testability of these networks under the Stuck-atfault model, and show how fully testable circuits can be generated from them by adding at most a constant number of multiplexer gates.

Fully Robust Path Delay Fault Testability using KEPSOP

“…Bounded multi level EXSOP (7), OR-AND-OR (8), SPP (9) &EPSOP(8&1)and the bound promising for high quality but huge minimization time required for their synthesis. KEP-SOP form minimization, an approximation algorithm which guarantee near optimum solution with polynomial time and utilize the projection of SOP form into subspaces of Boolean space that reduces the hamming distance among the cube appearing in each subspaces (1). BDD based optimization for Path Delay Fault Testability (10).Testability of KEP-SOP networks under the stuck-at-fault(11) uses Mux is 100% testable but the some network is not delay fault testable under the robust path delay model because the multiplexer will destroyed the testability of the network.…”

“…BDD based optimization for Path Delay Fault Testability (10).Testability of KEP-SOP networks under the stuck-at-fault(11) uses Mux is 100% testable but the some network is not delay fault testable under the robust path delay model because the multiplexer will destroyed the testability of the network. In our new approach will maintain the robust delay fault testability and whole design work on Functional mode with one control signals.In Section 2, the delay fault testability of network which explain the K-EPSOP form realization and projections of Boolean terms into the different spaces [1] and its implications on testability preservation. The pdf testability property using mux [11], BDD optimization [10],multi-valued minimization with PLA & output EXOR gate [5] and BDD based synthesis of symmetric circuit [9].…”