An approximate timing analysis method for datapath circuits

Yalcin, Hakan; Hayes, John P.; Sakallah, K.A.

doi:10.1109/iccad.1996.569410

Cited by 19 publications

(9 citation statements)

References 10 publications

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“…Multiple transitions at node 'b' activates this traditional false path. Using the method given in [3,15], the critical delay for the combinational module found to be 5 which is not the actual critical delay for this circuit. We observe that these methods ignore the simultaneous switching since S3,h,y is reported as a false path.…”

Section: Motivating Examplementioning

confidence: 94%

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Timing Analysis of Sequential Circuits Using Symbolic Event Propagation

Mondal

Chakrabarti

Dasgupta

2007

2007 International Conference on Computing: Theory and Applications (ICCTA'07)

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Accurate timing information of circuits is essential for high quality designs. This paper presents a symbolic event propagation based method to determine the critical delay of digital circuits. The proposed approach considers the effect of glitches, multiple transitions and simultaneous switching on the critical delay. Our method identifies and eliminates both combinational and sequential false paths. We also consider triggering of traditional combinational false paths due to multiple transitions. The mathematical formulation makes no assumption about the start state of the finite state machine extracted from the sequential circuit. Few approximate methods have been proposed to determine the upper bound of the critical delay. A complete BDD based implementation has been made. Results on ISCAS89 benchmark circuits are presented.

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Section: Motivating Examplementioning

confidence: 94%

“…These analyzers very often consider only the steady state value of a node. The path S1,t,c,y is reported as false path by the method given in [3,15]. Multiple transitions at node 'b' activates this traditional false path.…”

Section: Motivating Examplementioning

confidence: 99%

Timing Analysis of Sequential Circuits Using Symbolic Event Propagation

Mondal

Chakrabarti

Dasgupta

2007

2007 International Conference on Computing: Theory and Applications (ICCTA'07)

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“…The effectiveness of the method is demonstrated on a high level model of ISCAS-85 circuit C6288 which is difficult to analyze using traditional approaches. Based on the CDMs introduced in [5] an approximate timing analysis method for Data path Circuits is presented in [6].…”

Section: Introductionmentioning

confidence: 99%

Timing analysis of combinational circuits using Weights Binary Decision Diagram (WBDD)

Bhuvaneswari

Prasad

Singh

et al. 2010

2010 International Conference on Electronic Devices, Systems and Applications

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Weights Binary Decision Diagram (WBDD) based timing analysis of combinational circuit is proposed. Here we express the combinational circuit as a directed graph. We compute and store the delay of combinational circuits for all combination of inputs for the range of delay values based on controlling values. Hence it is possible to look up the built in library and calculate the output delay of any combinational circuit. The output delay computation is much faster when compared to normal method of calculating the delay at each level of the combinational circuits. This can be used in the synthesis of network for low power consumption.

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“…This is typical of datapath circuits, where a small number of control inputs determine the delays between a large number of data inputs and the outputs. Methods which successfully trade accuracy for computation using this approach have been reported in the literature [6,11].…”

Section: Introductionmentioning

confidence: 99%

Functional timing analysis for IP characterization

Yalcin

Mortazavi

Palermo

et al. 1999

Proceedings of the 36th Annual ACM/IEEE Design Automation Conference

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A method that characterizes the timing of Intellectual Property (IP) blocks while taking into account IP functionality is presented. IP blocks are assumed to have multiple modes of operation specified by the user. For each mode, our method calculates IO path delays and timing constraints to generate a timing model. The method thus captures the mode-dependent variation in IP delays which, according to our experiments, can be as high as 90%. The special manner in which delay calculation is performed guarantees that IP delays are never underestimated. The resulting timing models are also compacted through a process whose accuracy is controlled by the user.

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An approximate timing analysis method for datapath circuits

Cited by 19 publications

References 10 publications

Timing Analysis of Sequential Circuits Using Symbolic Event Propagation

Timing Analysis of Sequential Circuits Using Symbolic Event Propagation

Timing analysis of combinational circuits using Weights Binary Decision Diagram (WBDD)

Functional timing analysis for IP characterization

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