An approach to energy-error tradeoffs in approximate ripple carry adders

Kedem,; Mooney,; Muntimadugu,; Palem,

doi:10.1109/islped.2011.5993638

Cited by 21 publications

(28 citation statements)

References 12 publications

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“…That model requires a high level of redundancy (about 10 3 -10 4 ) that seems unrealistic. Since then, a number of imprecise circuits have been designed for different purposes in various levels of circuit and logic [35], architecture [25], data flow [24] and system. Depending on the desire application, approximate calculations exploit a trade-off between accuracy, efficiency and power consumption.…”

Section: Related Workmentioning

confidence: 99%

“…Some methods use approximate computing to come up with low-power designs. These methods are voltage over scaling (VOS) [11,26,45,55], biased VOS (BIVOS) [5,6,13,34,42,44], bit width reduction [15,50,54], cutting lower significant parts [36] and hardware simplification [16,21,36,42,43,59]. Majority of these techniques focused on adders, multipliers and their derivative systems.…”

Section: Related Workmentioning

confidence: 99%

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Approximate Arithmetic for Low-Power Image Median Filtering

Monajati

Fakhraie

Kabir

2015

Circuits Syst Signal Process

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In applications related to human senses, such as audio and image processing, computations with limited precision are acceptable. In these areas, a digital system can be implemented using approximate computing that works with sufficient precision. In this paper, we present a method to design 2-bit approximate magnitude comparators that are effectively low cost in terms of power, area and speed. We build larger comparators with adjustable error characteristics. Compared to precise one, our approximate comparators can save power and area up to 7-46 % and 10-50 %, respectively. The structures of our comparators and their error characteristics are presented in this paper. We use these comparators to design different approximate image median filters in order to remove salt and pepper noise. Simulation results show that the output quality of these filters is very similar to that of the precise ones so that the degradation is not noticeable. The approximate filters save up to 30 % of power and area while working 18 % faster than the precise ones.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Approximate Arithmetic for Low-Power Image Median Filtering

Monajati

Fakhraie

Kabir

2015

Circuits Syst Signal Process

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“…proposed in [1]. A general strategy for pruning out statisticallyunimportant logic nodes is studied in [6], [3].…”

Section: Introductionmentioning

confidence: 99%

Modeling and synthesis of quality-energy optimal approximate adders

Jin

Gerstlauer

et al. 2012

Proceedings of the International Conference on Computer-Aided Design

104

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Recent interest in approximate computation is driven by its potential to achieve large energy savings. This paper formally demonstrates an optimal way to reduce energy via voltage over-scaling at the cost of errors due to timing starvation in addition. We identify a fundamental trade-off between error frequency and error magnitude in a timing-starved adder. We introduce a formal model to prove that for signal processing applications using a quadratic signal-to-noise ratio error measure, reducing bit-wise error frequency is sub-optimal. Instead, energy-optimal approximate addition requires limiting maximum error magnitude. Intriguingly, due to possible error patterns, this is achieved by reducing carry chains significantly below what is allowed by the timing budget for a large fraction of sum bits, using an aligned, fixed internal-carry structure for higher significance bits.We further demonstrate that remaining approximation error is reduced by realization of conditional bounding (CB) logic for lower significance bits. A key contribution is the formalization of an approximate CB logic synthesis problem that produces a rich space of Pareto-optimal adders with a range of quality-energy tradeoffs. We show how CB logic can be customized to result in overand under-estimating approximate adders, and how a dithering adder that mixes them produces zero-centered error distributions, and, in accumulation, a reduced-variance error. We demonstrate synthesized approximate adders with energy up to 60% smaller than that of a conventional timing-starved adder, where a 30% reduction is due to the superior synthesis of inexact CB logic. When used in a larger system implementing an image-processing algorithm, energy savings of 40% are possible.

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“…This work demonstrated that greater power efficiency could be obtained because the errors rarely occurred, in which case the voltage could be overscaled. Similarly, a non-uniform voltage scaling technique was discussed in [3], which analysed the link between probability of output correctness and energy saving. While the voltage scaling literature takes advantage of the fact that only specific input patterns could cause timing errors, research on imprecise architectures take this one step further by taking advantage of errors only occurring with specific input patterns to design a simplified circuit.…”

Section: Introductionmentioning

confidence: 99%

Overclocking datapath for latency-error tradeoff

Shi

Boland

Constantinides

2013

2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)

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Abstract-Relaxing constraints of 100% accuracy in datapath can provide the freedom to create designs with better performance or energy efficiency. This paper develops probabilistic models, which enable us to explore these trade-offs for key arithmetic primitives. We show that because specific input patterns are required to cause timing violations and that these patterns arise rarely, a lower expected error can be attained by allowing some timing variations to occur, instead of reducing the precision of a circuit to meet a target latency. Experiments show that a mean reduction of 5.6× ∼ 36.7× in error expectation and an improvement of 7.2 ∼ 19.7 in signal-to-noise ratio can be obtained for practical applications.

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An approach to energy-error tradeoffs in approximate ripple carry adders

Cited by 21 publications

References 12 publications

Approximate Arithmetic for Low-Power Image Median Filtering

Approximate Arithmetic for Low-Power Image Median Filtering

Modeling and synthesis of quality-energy optimal approximate adders

Overclocking datapath for latency-error tradeoff

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