An Application of Cathodoluminescence to Optimize the Shallow Trench Isolation Process

Mizukoshi, T.; Shibusawa, K.; Yo, S.; Sugie, Ryuichi; Ajioka, T.

doi:10.1109/tsm.2005.858497

Cited by 7 publications

(3 citation statements)

References 12 publications

(9 reference statements)

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“…x 0 ¼ 1 ffiffi ffi 2 p ðÀ1; 1; 0Þ; y 0 ¼ ð0; 0; 1Þ; z 0 ¼ 1 ffiffi ffi 2 p ð1; 1; 0Þ; (7) and biaxial stress r 0 11 along the x 0 direction (horizontal direction) and r 0 22 along the y 0 direction (perpendicular direction) on a (110) face, Raman frequency shift Dx is written as 25,26 …”

Section: B Frequency Shift and Stress On A Cross-sectional Surfacementioning

confidence: 99%

“…For example, the dislocations induced by the stress from a shallow trench isolation (STI) structure are known to cause junction leakage current. [4][5][6][7][8] Moreover, in three-dimensional (3D) stacked ICs connected by through-Si vias (TSVs), the reliability tends to decrease and the risk of failure increases because of their internal residual stress originating from their relatively complex manufacturing process.…”

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confidence: 99%

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Measurement of temperature-dependent stress in copper-filled silicon vias using polarized Raman spectroscopy

Sugie

Kosaka

Seki

et al. 2013

Journal of Applied Physics

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An experimental method to determine the temperature dependence of residual stress in threedimensional (3D) structures was developed using polarized Raman spectroscopy. Stresses of a copper-filled silicon via at three temperatures, 223, 298, and 413 K were derived by measuring the frequency shift of the optical phonons through the backscattering geometry from the cross-section of the structure and assuming non-isotropic biaxial (horizontal and depth) stresses on the crosssection. Both stress components changed from tensile to compressive in almost all areas as the temperature changed from 213 to 413 K. The absolute stress values increased at both low and high temperatures and were smallest at 298 K, which was nearest to the process temperature of copper filling by plating. The main cause of stress is considered to be the difference in the coefficient of thermal expansion between copper and silicon. These results indicate that the temperature dependence of stress of copper-filled vias is affected mainly by their fabrication temperature. Process temperature is one of the key factors for the reduction of thermal stress in 3D structures such as integrated circuits connected by through-silicon vias. V C 2013 AIP Publishing LLC.

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Section: B Frequency Shift and Stress On A Cross-sectional Surfacementioning

confidence: 99%

mentioning

confidence: 99%

Measurement of temperature-dependent stress in copper-filled silicon vias using polarized Raman spectroscopy

Sugie

Kosaka

Seki

et al. 2013

Journal of Applied Physics

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“…9) We applied the CL technique to the study of LSI devices and showed that dislocation-related luminescence lines (D lines) in regions surrounding memory cells correlate with the standby leakage current of LSI devices. 10,11) In this study, we applied cross-sectional CL measurements to the study of electron-irradiated silicon IGBTs after annealing at 200 -400 C and investigated the spatial distribution and temperature dependence of radiative recombination centers. We discuss the relationship of static and dynamic electrical characteristics with radiative recombination centers.…”

Section: Introductionmentioning

confidence: 99%