An anomalous increase of threshold voltages with shortening the channel lengths for deeply boron-implanted N-channel MOSFET's

Nishida, M.; Onodera, Hidetoshi

doi:10.1109/t-ed.1981.20494

Cited by 41 publications

(9 citation statements)

References 5 publications

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“…Although much attention has been paid to this effect, its physical origin is still debated. Two approaches are currently advanced for its explanation either based on an enhanced oxide charge density near source and drain [45][46][47][48] or on a non uniform doping distribution along the channel [49][50][51][52][53][54][55][56], both being induced by the fabrication processes.…”

Section: Reverse Short Channel Effect (Rsce)mentioning

confidence: 99%

Device Physics and Electrical Performance of Bulk Silicon Mosfets

Ghibaudo¹

2001

Device and Circuit Cryogenic Operation for Low Temperature Electronics

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Section: Reverse Short Channel Effect (Rsce)mentioning

confidence: 99%

Device Physics and Electrical Performance of Bulk Silicon Mosfets

Ghibaudo¹

2001

Device and Circuit Cryogenic Operation for Low Temperature Electronics

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“…It remains to be seen, however, whether the effect is due to increased oxide thickness at the edge of the gate as suggested by Hsia et aZ. [8] or to the heavy threshold control implant as suggested by Nishida et al [9] and Fu et al The thresholds of devices with gate lengths less than 0.8 pm begin to drop with gate length when the MOSFET's are biased with a drain voltage of 5 V. This effect of drain voltage on the MOSFET threshold has been discussed in the literature [ l l ] , [12] . Fig.…”

Section: Process Descriptionmentioning

confidence: 99%

0.4-µm gate-length devices fabricated by contrast-enhanced lithography

Griffing

West

Heath

1983

IEEE Electron Device Lett.

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This letter describes the fabrication of submicrometer polysilicon-gate MOS devices by an advanced optical process called contrast enhancement. Functional devices having gate lengths as small as 0.4 pm.were fabricated with this process. Contrast-enhanced lithography (CEL) allows usable photoresist patterns to be fabricated at smaller dimensions than is possible with conventional resist. The simultaneous replication of mask dimensions for isolated lines at 0.35 pm and above was achieved in this work using a single exposure on an Optimetrix 1O:l DSW system. Contrast enhancement has been applied to the fabrication of n-channel MOS devices having gate lengths from 0.4 to 1.5 pm in steps of 0.1 pm. Long-channel devices were also fabricated. The transconductance of the 0.4-pm devices is 40 mS/mm at vds = 5 V. Threshold voltages (I/& = 0) are nearly independent of gate length, ranging from 1.21 to 1.31 V over the 7.5-to 0.4-pm range in gate length. The effective mobility for long-channel devices is 430 cm*/V . s. Contrast Enhanced Photoresist Conventional Photoresist 1 0~ Line w

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“…It can be reduced or can be even reversed (then it is called reverse short channel effect or RSCE) by locally raising the channel doping near source and drain junctions. RSCE was originally observed in MOSFETs due to oxidation-enhanced-diffusion [2] or implant-damageenhanced diffusion [3]. Lateral channel engineering utilizing halo or pocket implant [4][5][6][7][8] surrounding the source and drain regions is effective in suppressing SCE.…”

Section: Introductionmentioning

confidence: 99%

Low frequency drain current flicker noise model for pocket implanted nano scale n-MOSFET

Bhuyan

Khosru

2010

2010 IEEE Nanotechnology Materials and Devices Conference

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This paper presents an analytical drain current flicker noise model for pocket implanted nano scale n-MOSFET. The model is developed by using two linear pocket profiles at the source and drain edges. Thus the channel is divided into three regions at source, drain and central part of the channel region. Then the number of channel charges are found for these three regions and are incorporated it in the unified flicker noise model developed by Hung et al. for the conventional metal oxide semiconductor field effect transistor. The simulation results show that the derived drain current flicker noise model has a simple compact form. Index Terms -Pocket Implanted n-MOSFET, Flicker Noise.

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An anomalous increase of threshold voltages with shortening the channel lengths for deeply boron-implanted N-channel MOSFET's

Cited by 41 publications

References 5 publications

Device Physics and Electrical Performance of Bulk Silicon Mosfets

Device Physics and Electrical Performance of Bulk Silicon Mosfets

0.4-µm gate-length devices fabricated by contrast-enhanced lithography

Low frequency drain current flicker noise model for pocket implanted nano scale n-MOSFET

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