An analytical model relating FPGA architecture and place and route runtime

Chin, Scott Y. L.; Wilton, Steven J. E.

doi:10.1109/fpl.2009.5272519

Cited by 14 publications

(7 citation statements)

References 9 publications

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“…These effects have been observed experimentally [17] and expressed analytically [6]. Of course, increasing logic block size will increase the runtime of the CAD stages that map logic to these blocks.…”

Section: Why Logic Block Size Affects Runtimementioning

confidence: 83%

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Towards scalable FPGA CAD through architecture

Chin

Wilton

2011

Proceedings of the 19th ACM/SIGDA International Symposium on Field Programmable Gate Arrays

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Long FPGA CAD runtime has emerged as a limitation to the future scaling of FPGA densities. Already, compile times on the order of a day are common, and the situation will only get worse as FPGAs get larger. Without a concerted effort to reduce compile times, further scaling of FPGAs will eventually become impractical.Previous works have presented fast CAD tools that tradeoff quality of result for compile time. In this paper, we take a different but complementary approach. We show that the architecture of the FPGA itself can be designed to be amenable to fast-compile. If not done carefully, this can lead to lower-quality mapping results, so a careful tradeoff between area, delay, power, and compile run-time is essential. We investigate the extent to which run-time can be reduced by employing high-capacity logic blocks. We extend previous studies on logic block architectures by quantifying the area, delay and CAD runtime trade-offs for large capacity blocks, and also investigate some multi-level logic block architectures. In addition, we present an analytically derived equation to guide the design of logic block I/O requirements.

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Section: Why Logic Block Size Affects Runtimementioning

confidence: 83%

“…We considered three values for the second level hierarchy size (N 2=2, 4,6) and vary N 1 accordingly. Inputs at each level were chosen based on Equation 4 using a Rent parameter of p=0.8.…”

Section: Multi-level Logic Blocksmentioning

confidence: 99%

Towards scalable FPGA CAD through architecture

Chin

Wilton

2011

Proceedings of the 19th ACM/SIGDA International Symposium on Field Programmable Gate Arrays

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“…Moreover, as these models do not require extensive CAD flow, they are very efficient in evaluating hypothetical architectures. Models with respect to several metrics such as wirelength [6], critical path delay [4], [5] place and route run time [3], routability [1], channel width [2], and area [4] have been recently proposed in the literature. These analytical models can be further classified depending on the architecture on which they are based on.…”

Section: B Analytical Modelsmentioning

confidence: 99%

“…1b. Many quality metrics such as routability [1], channel width [2], place and route run time [3], critical path delay [4], [5] area [4] and wirelength [6] have been modelled with respect to the FPGA architectural parameters. FPGAs have been shown to consume on an average 12 times more power than ASICs [7].…”

Section: Introductionmentioning

confidence: 99%

An analytical energy model to accelerate FPGA logic architecture investigation

Rajavel

Akoglu

2011

2011 International Conference on Field-Programmable Technology

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There is a pressing need for exploring innovative reconfigurable architectures with the steady growth in the range of FPGA based applications. However, traditional FPGA architecture design methods require time consuming CAD experimentations to identify the most suitable hardware configuration for the target application. Several analytical models have been recently proposed to predict the relative performance of a given set of architectures. Replacing CAD experiments with these analytical models poses as the solution for reducing the complexity of architecture evaluation process. However, among a large set of existing models, an analytical energy model is missing to supplement the architecture evaluation. We argue that energy can be defined as a function of routed wire length and critical path delay. Therefore, we inherit wire length and critical path delay models to derive an analytical energy model for homogeneous FPGA architectures. We evaluate the impact of variations in logic architecture parameters in terms of LUT size, cluster size and inputs per CLB on the energy performance, and show that our energy model accurately captures the trends observed through CAD experiments. An energy model is robust only if its predictions are in agreement with any CAD flow or benchmark suite. We study the robustness of our energy model by varying the seed selection process of placement, optimization goal of clustering and placement, and the nature of the benchmark suite. In all our experimental evaluations, we observe that the energy model accurately captures the performance trends with a high degree of fidelity.

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“…Another drawback is that the signals have to be selected before compilation. Hence, observing a new subset of signals requires the circuit to be re-instrumented and recompiled, a process that can take hours [6]. Additionally, the insertion of the debug circuitry and the preselection of signals can alter the place and route of the design and can potentially create other problems, such as the user circuit may no longer fit in the FPGA device, or artificial timing limitations caused by the debugging circuitry.…”

Section: Introductionmentioning

confidence: 99%

Efficient Hardware Debugging Using Parameterized FPGA Reconfiguration

Kourfali

Stroobandt

2016

2016 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)

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Abstract-Functional errors and bugs inadvertently introduced at the RTL stage of the design process are responsible for the largest fraction of silicon IC re-spins. Thus, comprehensive functional verification is the key to reduce development costs and to deliver a product in time. The increasing demands for verification led to an increase in FPGA-based tools that perform emulation. These tools can run at much higher operating frequencies and achieve higher coverage than simulation. However, an important pitfall of the FPGA tools is that they suffer from limited internal signal observability, as only a small and preselected set of signals is guided towards (embedded) trace buffers and observed. This paper proposes a dynamically reconfigurable network of multiplexers that significantly enhance the visibility of internal signals. It allows the designer to dynamically change the small set of internal signals to be observed, virtually enlarging the set of observed signals significantly. These multiplexers occupy minimal space, as they are implemented by the FPGA's routing infrastructure.

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An analytical model relating FPGA architecture and place and route runtime

Cited by 14 publications

References 9 publications

Towards scalable FPGA CAD through architecture

Towards scalable FPGA CAD through architecture

An analytical energy model to accelerate FPGA logic architecture investigation

Efficient Hardware Debugging Using Parameterized FPGA Reconfiguration

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