An analytical energy model to accelerate FPGA logic architecture investigation

Abstract

There is a pressing need for exploring innovative reconfigurable architectures with the steady growth in the range of FPGA based applications. However, traditional FPGA architecture design methods require time consuming CAD experimentations to identify the most suitable hardware configuration for the target application. Several analytical models have been recently proposed to predict the relative performance of a given set of architectures. Replacing CAD experiments with these analytical models poses as the solution for reducing the complexity of architecture evaluation process. However, among a large set of existing models, an analytical energy model is missing to supplement the architecture evaluation. We argue that energy can be defined as a function of routed wire length and critical path delay. Therefore, we inherit wire length and critical path delay models to derive an analytical energy model for homogeneous FPGA architectures. We evaluate the impact of variations in logic architecture parameters in terms of LUT size, cluster size and inputs per CLB on the energy performance, and show that our energy model accurately captures the trends observed through CAD experiments. An energy model is robust only if its predictions are in agreement with any CAD flow or benchmark suite. We study the robustness of our energy model by varying the seed selection process of placement, optimization goal of clustering and placement, and the nature of the benchmark suite. In all our experimental evaluations, we observe that the energy model accurately captures the performance trends with a high degree of fidelity.

Analytical performance model for FPGA-based reconfigurable computing

“…Similar to dynamic power, leakage power, , can be represented as the sum of logic and routing parts as expressed by (13) where Plk.logic and Plk.route are computed based on (14) and (16), respectively.…”

“…, and the power of switch boxes, , as expressed in (16). These boxes consist of multiplexers, output buffers and SRAMs.…”

“…Reverse biased junction band-to-band-tunneling leakage (BTBT) power, is not taken into account and the model does not take the dynamic power into account. In [16], the authors indicated that energy can be defined as a function of routed wire length and critical path delay. Therefore, they used existing wire length and critical path delay models to derive an analytical energy model for FPGAs.…”