An analytical grain-barrier height model and its characterization for intrinsic poly-Si thin-film transistor

Chen, Hsin-Li; Wu, Chhi‐Chong

doi:10.1109/16.725260

Cited by 38 publications

(6 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Here, n d represents the usual channel doping and the second term represents the additional fixed volume space-charge density near the surface, L g is the grain size and n st is the grain boundary trap density of electrons. Baccarani et al [6] analysed the effect of distributed trap levels and found the monoenergetic trap model to match with experimental results and this has also been adopted by many other authors [7,8] to successfully model the poly-Si TFT. In our analysis also the monoenergetic trap model is adopted.…”

Section: Subthreshold Currentmentioning

confidence: 96%

Subthreshold conduction in short-channel polycrystalline-silicon thin-film transistors

Chopra

Gupta

2000

Semicond. Sci. Technol.

View full text Add to dashboard Cite

A model that characterizes the subthreshold regime and the threshold voltage of a short-channel polycrystalline silicon thin-film transistor (poly-Si TFT) is developed and supported experimentally. The subthreshold variations with gate and drain voltages are reported and a stronger drain voltage dependence is observed. The subthreshold swing is calculated and its variation with channel length and doping concentration is studied. The results are compared with the available experimental data and a good match is found. The temperature dependence of subthreshold swing and drain current is also shown. The channel length dependent proposed threshold voltage shows excellent agreement with experimental data.

show abstract

Section: Subthreshold Currentmentioning

confidence: 96%

Subthreshold conduction in short-channel polycrystalline-silicon thin-film transistors

Chopra

Gupta

2000

Semicond. Sci. Technol.

View full text Add to dashboard Cite

show abstract

“…Recently, three-dimensional (3D) stack NAND flash memories such as SMArT, 1,2) P-BiCS, [3][4][5][6] TCAT 7,8) and vertical gate, [9][10][11] which consists of the thin film polysilicon (poly-Si) channel [12][13][14] have been introduced to be the most promising near-term solution to over-come scaling challenges in conventional planar NAND flash memories. [15][16][17][18][19][20] However, as 3D vertical-NAND (V-NAND) flash memories shrink nonideal characteristics and performance degradation of the memory have been consistently reported.…”

Section: Introductionmentioning

confidence: 99%

Improvement of cell characteristics using controlling the current path in 3D NAND flash

Park

Lee

CHO

et al. 2023

Jpn. J. Appl. Phys.

View full text Add to dashboard Cite

In vertical-NAND (V-NAND) flash memory, the effect of current path change according to the program state was analyzed. A new memory structure in which a heavily doped polysilicon layer is added around a typical V-NAND channel was proposed, and electrical characteristics were observed through simulation. As a result, it was confirmed that the electrical characteristics such as Vth and S.S of V-NAND can be changed and that the current path can be adjusted. Through an experiment to change the doping concentration of the added doping area, there was a sudden change in the current path at 5.0  1017/cm3and 5.2  1017/cm3during boron doping. The change of the current path was observed at this rapidly changing point, and the device characteristics could be dramatically improved if the current path was changed by adding an extra doping region. Additionally, the effects of program operating voltage conditions and doping type changes on V-NAND operation were analyzed.

show abstract

“…Furthermore, the GB barrier heights were evaluated in MWA and HPHA devices to reveal the mobility enhancement effect of each process [11]. The GBT density can also be inferred, as the GB barrier height is proportional to its square [27]. In addition, the crystallization effect of MWA was verified using Raman spectroscopy.…”

Section: Introductionmentioning

confidence: 99%

Synergy effect of microwave annealing and high-pressure hydrogen annealing on Poly-Si thin-film transistor

Lee¹,

Lee²,

Lee³

et al. 2022

Nanotechnology

View full text Add to dashboard Cite

Grain boundary (GB) is a significant factor that deteriorates the transfer characteristics of poly Si thin-film transistors (TFTs). In this study, we utilized the synergistic effect of microwave annealing (MWA) and high-pressure hydrogen annealing (HPHA) to effectively reduce grain boundary trap (GBT) density, resulting in improved field-effect mobility (μ) and subthreshold swing (SS). To investigate the synergistic effect of MWA and HPHA, the transfer characteristics of rapid thermal annealing (RTA) and forming gas annealing (FGA) devices were compared and analyzed as control devices. Furthermore, the mechanism of SS and mobility enhancement can be quantitatively understood by lowering the GB barrier height. In addition, Raman spectroscopy proved that poly-Si crystallinity was improved during MWA. Our results showed that MWA and HPHA play a vital role in reducing GBT density and improving poly-Si TFT characteristics.

show abstract

An analytical grain-barrier height model and its characterization for intrinsic poly-Si thin-film transistor

Cited by 38 publications

References 8 publications

Subthreshold conduction in short-channel polycrystalline-silicon thin-film transistors

Subthreshold conduction in short-channel polycrystalline-silicon thin-film transistors

Improvement of cell characteristics using controlling the current path in 3D NAND flash

Synergy effect of microwave annealing and high-pressure hydrogen annealing on Poly-Si thin-film transistor

Contact Info

Product

Resources

About