An Analytical Drain Current Model of Gate-On-Source/Channel SOI-TFET

Mitra, Suman Kr.; Bhowmick, Brinda

doi:10.1007/s12633-019-0090-7

Cited by 10 publications

(3 citation statements)

References 24 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The proposed network consists of 3 hidden layers with configuration (15,15,9). 15 neurons in the first hidden layer, 15 neurons in the second hidden layer and 9 neurons in the last hidden layer.…”

Section: E U Bmentioning

confidence: 99%

“…[1][2][3][4][5][6][7] By developing these devices, many efforts have been done to provide different analytical models at different Spice levels to be used in electronic applications to assess the circuits. [8][9][10] Conducting silicon-based semiconductor technology to the nanoscale according to the roadmap has faced enormous challenges that will eventually require new electronic devices to maintain this roadmap. Graphene, a single atomic layer of graphite, is considered as one of the most interesting two-dimensional (2D) materials that can be replaced by silicon-based devices.…”

mentioning

confidence: 99%

See 1 more Smart Citation

Graphene Nanoribbon FET Compact Model on the Basis of ANN Configuration Applicable in Different Spice Levels

Anvarifard

Ramezani

Amiri

2021

ECS J. Solid State Sci. Technol.

View full text Add to dashboard Cite

The artificial neural networks (ANNs) are widely utilized as a powerful approximator for a vast number of complicated nonlinear functions in many fields in different domains. Multi-layer perceptron (MLP) as a unique strategy in this work has been highlighted making an analytical drain current prediction of graphene nanoribbon field-effect transistor (GNRFET) simple and efficient having a linear dependence on the fundamental variables. The MLP structure in this work is configured with three hidden layers and 5-dimensional inputs giving the best result after performing different experiments. Target output as the key parameter is actually the numerically calculated drain current by the Non-Equilibrium Green Function (NEGF) method which is commonly used for the simulation of nanoscale devices. The critical parameters in the cases of gate oxide thickness, gate length, number of carbon atoms across the channel, gate voltage, and drain voltage are selected as the dimensions of the input vector impacting the obtained drain current by the ANN. The comprehensive comparison between the NEGF approach and the proposed ANN-based model revealed an excellent match and correlation between them. As a result, this model can be taken into consideration as a suitable tool in the different spice levels owing to the saving the running time and also increase in the efficiency of nanoscale circuits based on the GNRFET structure.

show abstract

Section: E U Bmentioning

confidence: 99%

mentioning

confidence: 99%

Graphene Nanoribbon FET Compact Model on the Basis of ANN Configuration Applicable in Different Spice Levels

Anvarifard

Ramezani

Amiri

2021

ECS J. Solid State Sci. Technol.

View full text Add to dashboard Cite

show abstract

“…This paper focuses on the TID effect in SOI-TFET with oxide/source overlap, the structure of the device is described in Figure 1 . The gate of the device overlaps the oxide and the source can increase the on-state current [ 10 , 11 , 12 ], while the SOI structure can eliminate the latch-up effect and reduce parasitic capacitance [ 13 , 14 , 15 , 16 ]. It is found that the current switch ratio and subthreshold swing of the device deteriorates while threshold voltage has a slight drop, but it is not too sensitive after irradiation.…”

Section: Introductionmentioning

confidence: 99%

Research on Total Ionizing Dose Effect and Reinforcement of SOI-TFET

et al. 2021

View full text Add to dashboard Cite

Since the oxide/source overlap structure can improve the tunneling probability and on-state current of tunneling field effect transistor (TFET) devices, and the silicon-on-insulator (SOI) structure has the effect of resisting the single event effect, SOI-TFET with the oxide/source overlap structure is a device with development potential. The total ionizing dose (TID) effect on SOI-TFET was studied by discussing the switching ratio, band–band tunneling rate, threshold voltage, sub-threshold swing and bipolar effect of the device under different doses of irradiation. At the same time, simulations prove that selecting the proper thickness of the buried oxide (BOX) layer can effectively reduce the influence of the TID effect. This provides a way of direction and method for research on the irradiation effects on the device in the future.

show abstract

An analytical model for a TFET with an n-doped channel operating in accumulation and inversion modes

Ranjith

Komaragiri

2021

J Comput Electron

View full text Add to dashboard Cite

An Analytical Drain Current Model of Gate-On-Source/Channel SOI-TFET

Cited by 10 publications

References 24 publications

Graphene Nanoribbon FET Compact Model on the Basis of ANN Configuration Applicable in Different Spice Levels

Graphene Nanoribbon FET Compact Model on the Basis of ANN Configuration Applicable in Different Spice Levels

Research on Total Ionizing Dose Effect and Reinforcement of SOI-TFET

An analytical model for a TFET with an n-doped channel operating in accumulation and inversion modes

Contact Info

Product

Resources

About