An Analytical Delay Model for Mechanical Stress Induced Systematic Variability Analysis in Nanoscale Circuit Design

Alam, Naushad; Bulusu, Anand; Dasgupta, S.

doi:10.1109/tcsi.2013.2295028

Cited by 7 publications

(7 citation statements)

References 28 publications

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“…Based on the model, new effective SA/SB formulas have been derived to improve the simulation efficiency and have also been verified by data from various layouts. An analytical model to estimate the delay in the presence of process-induced mechanical stress in stacked transistors based inverters and logic gates has been reported by Alam et al 173 Derived using a modified alpha-power law, this model considers the channel length modulation effect. The methodology to incorporate the impact of processinduced mechanical stress effects in the derived delay model has also been presented.…”

Section: -10mentioning

confidence: 99%

Bending induced electrical response variations in ultra-thin flexible chips and device modeling

Heidari

Wacker

Dahiya

2017

Applied Physics Reviews

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Electronics that conform to 3D surfaces are attracting wider attention from both academia and industry. The research in the field has, thus far, focused primarily on showcasing the efficacy of various materials and fabrication methods for electronic/sensing devices on flexible substrates. As the device response changes are bound to change with stresses induced by bending, the next step will be to develop the capacity to predict the response of flexible systems under various bending conditions. This paper comprehensively reviews the effects of bending on the response of devices on ultra-thin chips in terms of variations in electrical parameters such as mobility, threshold voltage, and device performance (static and dynamic). The discussion also includes variations in the device response due to crystal orientation, applied mechanics, band structure, and fabrication processes. Further, strategies for compensating or minimizing these bending-induced variations have been presented. Following the in-depth analysis, this paper proposes new mathematical relations to simulate and predict the device response under various bending conditions. These mathematical relations have also been used to develop new compact models that have been verified by comparing simulation results with the experimental values reported in the recent literature. These advances will enable next generation computer-aided-design tools to meet the future design needs in flexible electronics.

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Section: -10mentioning

confidence: 99%

Bending induced electrical response variations in ultra-thin flexible chips and device modeling

Heidari

Wacker

Dahiya

2017

Applied Physics Reviews

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“…Table 3, Table 4 and Table 5 present the same data (also considering Tout50 estimation) for the approaches proposed by Rossello and Segura [10], by Wang and Zwolinski [12] and by Huang et al [22], respectively. Notice that two recent proposals presented in [25] and in [26] are not directly evaluated because these methods also neglect SCC, showing to similar errors as those observed in [12]. Consoli's approach, presented in [13] is also not directly evaluated since we found this model to be as accurate as Rossello's model [10].…”

Section: Single Inverter Evaluationmentioning

confidence: 76%

“…Wang and Zwolinski, in [12], consider channel length modulation but neglect SCC, and a closed formulation for inverter delay estimation is only presented when the input transition is considered fast. In [26], Alam et. al., consider channel length modulation although neglecting both SCC and I/O coupling capacitance.…”

Section: Differential Equation Solving Modelingmentioning

confidence: 99%

“…From the works on this group, only the approaches presented in [6], [8], [12], [13] and [26] consider channel length modulation and only the ones proposed in [8] and [13] take into account DIBL effect.…”

Section: Differential Equation Solving Modelingmentioning

confidence: 99%

“…In CMOS inverter delay analysis, only the gate-to-drain capacitance (Cgd) is a concern. Typically, Cgd is considered to be half the gate capacitance for a transistor operating in linear region and zero for a device with the channel pinch off or in off state [26]. Hence, the coupling capacitance for a static low input (Cm low ) can be written as follows:…”

Section: Preliminariesmentioning

confidence: 99%

See 2 more Smart Citations

Improving Analytical Delay Modelingfor CMOS Inverters

Marranghello¹,

Reis²,

Ribas³

2020

JICS

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Analytical methods for gate delay estimation are very useful to speedup timing analysis of digital integrated circuits. This work presents a novel approach to analytically estimate the CMOS inverter delay. The proposed method considers the influence of input slope, output load and I/O coupling capacitance, as well as relevant effects such as channel length modulation and drain induced barrier lowering. Experimental results are on good agreement with HSPICE simulations, showing significant accuracy improvement compared to published related work. The delay model error has an average value of 3%, and the worst case error is smaller than 10%.

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A variation aware timing model for a 2-input NAND gate and its use in sub-65 nm CMOS standard cell characterization

Kaur

Sharma

Alam

et al. 2016

Microelectronics Journal

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An Analytical Delay Model for Mechanical Stress Induced Systematic Variability Analysis in Nanoscale Circuit Design

Cited by 7 publications

References 28 publications

Bending induced electrical response variations in ultra-thin flexible chips and device modeling

Bending induced electrical response variations in ultra-thin flexible chips and device modeling

Improving Analytical Delay Modelingfor CMOS Inverters

A variation aware timing model for a 2-input NAND gate and its use in sub-65 nm CMOS standard cell characterization

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