Proceedings International Test Conference 2001 (Cat. No.01CH37260)
DOI: 10.1109/test.2001.966687
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An analysis of power reduction techniques in scan testing

Abstract: Power consumption during scan testing is becoming a concern. Circuit switching activity during scan shifting is high and results in high average and instantaneous power consumption. This paper presents a scheme for reducing power and provides analysis results on an industrial design.

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Cited by 140 publications
(97 citation statements)
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“…Nicolai and AlHashimi [21] proposed a technique to minimize useless switches, and Gerstendörfer and Wunderlich [5] introduced a technique to disconnect the scan-chains from the combinational logic during the shift process, both leading to a lower power consumption during test, which reduces test time by allowing clocking at a higher frequency. For the same purpose, Saxena et al [24] proposed an approach to gate sub-chains.…”
Section: Background and Related Workmentioning
confidence: 99%
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“…Nicolai and AlHashimi [21] proposed a technique to minimize useless switches, and Gerstendörfer and Wunderlich [5] introduced a technique to disconnect the scan-chains from the combinational logic during the shift process, both leading to a lower power consumption during test, which reduces test time by allowing clocking at a higher frequency. For the same purpose, Saxena et al [24] proposed an approach to gate sub-chains.…”
Section: Background and Related Workmentioning
confidence: 99%
“…The RPC (reconfigurable power-conscious) test wrapper we propose combines the gated sub-chain approach proposed by Saxena et al [24] and the reconfigurable wrapper introduced by Koranne [15]. The basic idea in the approach proposed by Saxena et al [24] is to use a gating scheme to lower the test power dissipation during the shift process.…”
Section: A Novel Reconfigurable Power-conscious Core Test Wrappermentioning
confidence: 99%
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