An Analysis Based on Fault Injection of Hardening Techniques for SRAM-Based FPGAs

Abstract

Triple Modular Redundancy (TMR) is recognized as one of the possible solutions to harden circuits implemented on SRAM-based FPGAs against soft-errors affecting configuration memory and user memory. Several works already showed cross-section figures confirming the soundness of TMR principle, however some faults still escape the TMR's fault masking mechanism. In this work we analyzed by means of extensive fault-injection experiments the TMR architecture. We identified some of the causes that are responsible for the escaped faults, and we proposed possible solutions. In our analyses we considered both the TMR and one of its enhanced version, the XTMR.

SEU Recovery Mechanism for SRAM-Based FPGAs

“…Table I provides a decomposition of the syndrome value and its corresponding error status. The first 11 bits of the syndrome value S identify the location of a single erroneous bit within the frame (including the errors in the parity bits), while the last bit of the syndrome value S [11] indicates a double error in the frame. Virtex 4 and Virtex 5 FPGA have an embedded ECC circuit that calculates the syndrome value during each frame readback.…”

A Simulation Platform for the Study of Soft Errors on Signal Processing Circuits through Software Fault Injection

“…• The Politecnico di Torino has developed a new partial reconfiguration-based fault injection system to evaluate the SEU effects in SRAM-based FPGAs [6] [7].…”

Model matching for asynchronous sequential machines with adversarial inputs using state bursts

“…Issues of modularity and energy consumption plead in favor of asynchronous solutions at the system level [2]. At the same time, due to their low power consumption and electromagnetic noise emission, asynchronous machines are gaining a strong foothold in safety-critical applications such as aviation electronics [3] and nuclear engineering [4]. As a result, of increasing importance is a method to detect and overcome potential malfunctions caused by an unauthorized and adversarial input agent that attempts to interfere with the proper operation of the asynchronous machine.…”