An All-Standard-Cell-Based Synthesizable SAR ADC With Nonlinearity-Compensated RDAC

Abstract

We propose an all-standard-cell-based synthesizable successive-approximation-register analog-to-digital converter (SAR ADC) which is automatically placed and routed (P&R) using a commercial digital implementation tool. For higher feasibility and wider input range, a differential architecture is proposed with an inverter-based resistive digital-to-analog converter (RDAC) and a four-input comparator. MOSFET gate capacitance is employed for the sampling capacitor. To mitigate its capacitance variation due to input voltage and the leakage between gate and diffusion, we leave the diffusion of the standard cell floating and only use the capacitance between gate and bulk. Two prototypes have been designed in 65-nm bulk CMOS. Prototype I has been fabricated and achieves 10 MS/s, 14.3 mW, and 28.1-dB SNDR in a 6-bit architecture. The performance is improved in Prototype II by proposing a lookup table (LUT)-compensating transistor-configurable inverter-based RDAC and an OR-AND-Inverter (OAI)-based comparator and by employing a thick-oxide diffusion-floating decoupling cell for the sampling capacitor. The default LUT is created during the design phase by a script-controlled automatic simulation routine. The power consumption is significantly reduced as well through improved timing control. Layout-parasitic-extraction (LPE) simulations of Prototype II suggest 35.7-and 47.2-dB SNDRs in 6-and 8-bit versions, respectively. The power consumptions are reduced to 0.91 and 2.52 mW, respectively.

All-Standard-Cell-Based Analog-to-Digital Architectures Well-Suited for Internet of Things Applications

“…Consequently, a residue voltage remained at the drain node that could be amplified during the next comparison, generating an error output. To resolve that, it was proposed to replace the NAND gates with OR-AND inverter (OAI) cells [6]. Thus, an explicit reset is performed on the drain nodes, eliminating the residue voltages and thereby reducing the probability of a wrong output.…”

“…Therefore, the use of digital circuits is becoming popular in analog or mixed-signal circuit design, such as in the case of ADCs. Consequently, synthesizable solutions using standard cells are used to further reduce redesign time and effort [6][7][8].…”

Design and Implementation of Scalable and Parametrizable Analog-to-Digital Converter on FPGA

“…A very recent SAR-based ADC is presented in [43], which improves the previous ADC, achieving 10 MSPS and 7.5 ENOB. The ADC is synthesizable in standard cell 65-nm CMOS technology, and it is based on an inverter-based RDAC (Resistive DAC), a compensating LUT and a OAI-based (or-and-inverter) comparator.…”

Standard-Cell-Based Comparators for Ultra-Low Voltage Applications: Analysis and Comparisons

“…A latched comparator is a circuit element that interfaces the analog to the digital world: its output is either a low or high logic level, according to the relationship between the input signal, sampled by the latching clock, and a reference threshold. Often, a differential input signal with an implicit zero reference level is used, but fully differential comparators that have explicit differential inputs both for the signal and for the reference are also used [1][2][3][4][5][6].…”

“…The usual approach to design standard-cell-based latched comparators starts from a NAND-based [3,[6][7][8]46] or NOR-based latch [50,51], and several designs have been presented in the literature to optimize different performances for applications in ADCs and LDOs [9,10,49,[52][53][54][55][56][57]. However, such applications typically focus on different performance parameters, hence proposed designs are not always easy to compare.…”