An Algorithm for the Design of Low-Power Hardware-Efficient FIR Filters

Aktan, Mustafa; Yurdakul, Arda; Dündar, Günhan

doi:10.1109/tcsi.2008.917997

Cited by 88 publications

(128 citation statements)

References 13 publications

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“…The design of low-power low-complexity FIR filters has been studied by several researchers [46,47]. This section discusses the impact of LNS on the implementation of FIR filters.…”

Section: Lns and Fir Filter Architecturesmentioning

confidence: 99%

Logarithmic Number System and Its Application in FIR Filter Design

Paliouras

2017

Embedded Systems Design With Special Arithmetic and Number Systems

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Data representation is an important parameter in the design of digital signal processors as it affects their performance and hardware complexity. Data representation influences the choice of algorithms and the hardware architecture, thus it has an impact on data storage requirements, processing performance, complexity, and power dissipation [1][2][3].The Logarithmic Number System (LNS) can be used to efficiently represent data in special-purpose processors. The efficiency of LNS stems from the properties of the logarithm exploited to reduce the basic arithmetic operations of multiplication, division, square roots, and squares to simple binary addition, subtraction, and right and left shifts, respectively [4]. Similarly, the computation of general roots and powers as well as of reciprocals are substantially simplified.Building on the reduced complexity of certain arithmetic operations, digital signal processor implementations can benefit from substantial architectural-level simplifications. Furthermore, beyond operation strength reduction, superior LNS dynamic range and numerical behavior, compared to conventional representations, are additional reasons that make LNS attractive. In order to fully utilize LNS potential, procedures are required to optimally define LNS design parameters and derive LNS solutions, matched to application specifications and requirements.

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“…The design of low-power low-complexity FIR filters has been studied by several researchers [46,47]. This section discusses the impact of LNS on the implementation of FIR filters.…”

Section: Lns and Fir Filter Architecturesmentioning

confidence: 99%

Logarithmic Number System and Its Application in FIR Filter Design

Paliouras

2017

Embedded Systems Design With Special Arithmetic and Number Systems

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“…As the coefficients of an application specific filter are constant, the decomposition is more efficient than employing multipliers. The complexity of FIR filters in this case is dominated by the number of additions/subtractions and multiplications [10]. The multiplier block of the digital FIR lter in its transposed form is implemented in the design so that signi cant impact on the complexity and performance of the design will be improved.…”

Section: IImentioning

confidence: 99%

Optimization technique of FIR filter using digit serial architecture

Rewatkar

Badjate²

2013

2013 International Conference on Green Computing, Communication and Conservation of Energy (ICGCE)

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Paper Present optimization technique of Low Power and Area of FIR filter using different architecture. This technique is necessary for filters while required different sampling rates. The proposed device is FIR filter, it design by different way so that circuit complexity will be reduced. Multiplier, adders and latches are reduced by different logic due to which power and area in system is reduced at great extend. The results for power and area in each case are verified and report is presented. Simulation of the design done by Active-HDL which verified and implemented successfully. Then it is synthesized by using 45 nm library in synopsis tool with constraint of low power and area. Reduction of power consumption is important parameter for system. In the last two decades, many efficient algorithms and architectures have been introduced for the design of low complexity operation. Authors have given attention to the digit serial design that offers alternative low complexity in operations. Experimental results have shown the efficiency of the proposed optimization technique and the design of digit serial operations due to which the power dissipation of FIR filter is reduced. Digit serial style is best suited for implementation of digital signal processing system which requires moderate sampling rates. In this paper, an alternative approach for the design of digit serial architecture is presented.Keywords: VLSI-Very large scale integrated circuit, RTL-Register transfer logic, DSP-Digital signal processing, VHDL-Very high speed hardware description language, FIR-Finite impulse response, Active-HDL-Active hardware descriptive language

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“…In both cases, and no negation of either or is required. The aforementioned incremental product is then computed as (5) (the LSB is neglected to retain the most significant bits of ), while for , we carry out the sign extension to have (6) Note that since at least one of the two bits is guaranteed to be zero, simple AND-OR logic rather than a full fledged full adder will be enough to generate , i.e., the ' ' operation occurring in the computation of will be a simple logical OR operation.…”

Section: The Proposed Implementationmentioning

confidence: 99%

A SPT Treatment to the Realization of the Sign-LMS Based Adaptive Filters

Choudhary

Mukherjee

Chakraborty

et al. 2012

IEEE Trans. Circuits Syst. I

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The "sum of power of two (SPT)" is an effective format to represent filter coefficients in a digital filter which reduces the complexity of multiplications in the filtering process to just a few shift and add operations. The canonic SPT is a special sparse SPT representation that guarantees presence of at least one zero between every two non-zero SPT digits. In the case of adaptive filters, as the coefficients are updated with time continuously, conversion to such canonic SPT forms is, however, required at each time index, which is quite impractical and requires additional circuitry. Also, as the position of the non-zero SPT terms in each coefficient word changes with time, it is not possible to carry out multiplications involving the coefficients via a few fixed "shift and add" operations. This paper addresses these problems, in the context of a SPT based realization of adaptive filters belonging to the sign-LMS family. Firstly, it proposes a bit serial adder that takes as input two numbers in canonic SPT and produces an output also in canonic SPT, which is then extended to the case where one of the inputs is given in 2's complement form. This allows weight updating purely in the canonic SPT domain. It is also shown how the canonic SPT property of the input can be used to reduce the complexity of the proposed adder. For multiplication, the canonic SPT word for each coefficient is partitioned into non-overlapping digit pairs and the data word is multiplied by each pair separately. The fact that each pair can have at the most one non-zero digit is exploited further to reduce the complexity of the multiplication.Index Terms-Bit serial realization, canonic SPT, sign-LMS algorithm, sum of power of two (SPT).

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An Algorithm for the Design of Low-Power Hardware-Efficient FIR Filters

Cited by 88 publications

References 13 publications

Logarithmic Number System and Its Application in FIR Filter Design

Logarithmic Number System and Its Application in FIR Filter Design

Optimization technique of FIR filter using digit serial architecture

A SPT Treatment to the Realization of the Sign-LMS Based Adaptive Filters

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