Optimization technique of FIR filter using digit serial architecture

Abstract

Paper Present optimization technique of Low Power and Area of FIR filter using different architecture. This technique is necessary for filters while required different sampling rates. The proposed device is FIR filter, it design by different way so that circuit complexity will be reduced. Multiplier, adders and latches are reduced by different logic due to which power and area in system is reduced at great extend. The results for power and area in each case are verified and report is presented. Simulation of the design done by Active-HDL which verified and implemented successfully. Then it is synthesized by using 45 nm library in synopsis tool with constraint of low power and area. Reduction of power consumption is important parameter for system. In the last two decades, many efficient algorithms and architectures have been introduced for the design of low complexity operation. Authors have given attention to the digit serial design that offers alternative low complexity in operations. Experimental results have shown the efficiency of the proposed optimization technique and the design of digit serial operations due to which the power dissipation of FIR filter is reduced. Digit serial style is best suited for implementation of digital signal processing system which requires moderate sampling rates. In this paper, an alternative approach for the design of digit serial architecture is presented.Keywords: VLSI-Very large scale integrated circuit, RTL-Register transfer logic, DSP-Digital signal processing, VHDL-Very high speed hardware description language, FIR-Finite impulse response, Active-HDL-Active hardware descriptive language