An algorithm for scaling and single residue error correction in residue number systems

Su, Chien-Chun; Lo, Hao‐Yung

doi:10.1109/12.57044

Cited by 32 publications

(19 citation statements)

References 18 publications

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“…The error detection and correction circuits for these schemes are very complicated and costly in both time and hardware [3], [7], [ 111, [19]. Once an error is located, the correction proceeds in an unchecking way although self-checking is used during the course of error detection [ 1 11, [ 121. To reduce the hardware cost, an algorithm that combines the operations of scaling and single residue error correction into one circuit were proposed in [29]. Although this reduces the hardware cost of the scaling and error correction circuit by using the same mixed radix conversion circuit, the entire circuit, which is called an error correction circuit with scaling (EECS), is not self-checking.…”

Section: S In Other Computations Reliable Computing Is Criticalmentioning

confidence: 99%

“…Most of the earlier efforts on fault-tolerant processor design have focused on the stages before the final residue decoder. These efforts assume that the residue decoder is more reliable than the other circuits and the correction circuits are error-free [6], [7], [12], [29]. However, this is not the case when the required output is a binary number which requires a residue decoder to combine the values from all moduli into one result and the correction circuit is built by the same technology as all the other circuits in the processor.…”

Section: A Fault-tolerant Processormentioning

confidence: 99%

“…However, this is not the case when the required output is a binary number which requires a residue decoder to combine the values from all moduli into one result and the correction circuit is built by the same technology as all the other circuits in the processor. Another shortcoming of these efforts is that they assume overflows and errors could not occur simultaneously [ll], [12], [29].…”

Section: A Fault-tolerant Processormentioning

confidence: 99%

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A fault-tolerant permutation network modulo arithmetic processor

Lin

Oruç

1994

IEEE Trans. VLSI Syst.

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Conventional fault-tolerant modulo arithmetic processors rely on the properties of a residue number system with L redundant moduli to detect up to L / 2 errors. In this paper, we propose a new scheme that combines r-out-of-s residue codes with Berger codes to concurrently detect any number of module errors without any redundant moduli. In addition, this scheme can tolerate L faults if L redundant moduli are used, and has the property of graceful degradation when the number of faulty moduli exceeds L. Finally, it is shown that the added cost for fault tolerance is much less than those were reported earlier in the literature.Index Terms-Concurrent error detection, fault tolerance, graceful degradation, module discard, modulo arithmetic processor, and permutation network.

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Section: S In Other Computations Reliable Computing Is Criticalmentioning

confidence: 99%

Section: A Fault-tolerant Processormentioning

confidence: 99%

Section: A Fault-tolerant Processormentioning

confidence: 99%

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A fault-tolerant permutation network modulo arithmetic processor

Lin

Oruç

1994

IEEE Trans. VLSI Syst.

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“…Hence, in many RNS applications such Aided Design (CAD) tool. The tool is implemented in C++ and its output is a synthesizable VHSIC Hardware Description Language (VHDL) code [7], which can be used as input in VLSI design systems.…”

Section: Introductionmentioning

confidence: 99%

A full adder based methodology for scaling operation in residue number system

Soudris

Dasygenis

Mitroglou

et al.

9th International Conference on Electronics, Circuits and Systems

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A systematic methodology for designing full-adder-based architectures in Residue Number System for scaling operation and its software tool development, are introduced. Starling from the mathematical description of scaling operation in RNS, we end up with the VHDL description of a full-adder based architecture. The proposed tool was implemented in C+t language and it is available for PC and HP Platforms. The derived architectures are characterized by smaller hardware complexity and higher throughput rates than existing ones.

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“…However, most of the previous works focus on single-residue error correction because of the considerations of large memory space requirement [2,8] or computational inefficiency [1,3-71. In our previous paper [9], we developed a coding thoery approach to error control in RRNS.…”

Section: Introductionmentioning

confidence: 99%

Fast Algorithms for Multiple Errors Detection and Correction in Redundant Residue Number Systems

Sun¹,

Krishna²

1990 Conference Record Twenty-Fourth Asilomar Conference on Signals, Systems and Computers, 1990.

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In this work, we s t u d y and extend t h e coding theory approach to error control in redundant residue number systems (RRNS). We derive new computationally emcient algorithms for correcting a n d detecting multiple errors.These algorithms reduce t h e computational complexity of t h e previously known a l g o r i t h m by a n order of magnitude. Also, it is worthwhile t o mention here t h a t all t h e literature published t h u s far deals almost exclusively with single error correction.

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An algorithm for scaling and single residue error correction in residue number systems

Cited by 32 publications

References 18 publications

A fault-tolerant permutation network modulo arithmetic processor

A fault-tolerant permutation network modulo arithmetic processor

A full adder based methodology for scaling operation in residue number system

Fast Algorithms for Multiple Errors Detection and Correction in Redundant Residue Number Systems

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