A full adder based methodology for scaling operation in residue number system

Abstract

A systematic methodology for designing full-adder-based architectures in Residue Number System for scaling operation and its software tool development, are introduced. Starling from the mathematical description of scaling operation in RNS, we end up with the VHDL description of a full-adder based architecture. The proposed tool was implemented in C+t language and it is available for PC and HP Platforms. The derived architectures are characterized by smaller hardware complexity and higher throughput rates than existing ones.

A 2 n scaling scheme for signed RNS integers and its VLSI implementation

“…However, the implementation costs of these LUT-based schemes will increase significantly when the dynamic range of RNS is large. In [13], a scaling algorithm based on full-adder structure was proposed, and its scaling factor is the product of several moduli. In [14], Burgess introduced a new core function based scaling algorithm, in which the product of several moduli is used as the scaling factor and its magnitude is approximate √ P .…”

“…According to the types of scaling factors, RNS scaling can be classified into three groups: scaling by one modulus or the product of several moduli [6,7,9,[11][12][13][14], the scaling factor being coprime with the moduli of RNS [8], and scaling by the power of two [10,15]. The specific implementation techniques for scaling fall into two categories: Combinational logic [10,13,14] and LUT (or the mixture of these two techniques) [6-9, 11, 12, 15]. With respect to the fundamentals of the algorithm in scaling, there are three main types: CRT combined with MRC [6,11], CRT [7-10, 12, 15] and core function [14].…”

RNS Scaling Algorithm for a New Moduli Set {2^(2n+1) +1, 2^(2n+1), 2^(2n+1)-1}

“…Most scaling schemes reported in the literature are based on LUTs, and none of the papers discussed the order of generation of scaled residues until 2007 [24]. Almost all publications have agreed that LUTs are more efficient for small inputs, as in image processing applications, while a FA-based structure is well suited for long inputs [3]. Extensive measurements in area, delay and hardware utilization for full-adder-based designs have been proposed.…”

“…This advantage is as a result of the carry propagation problem in binary number systems [3]. Performing calculations in an RNS based system leads to less delay in processing time (clock cycles), reduction in the cost of hardware resources and power consumption [4].…”

Σχεδιασμός Πολύπλοκων Ενσωματωμένων Συστημάτων Με Χαμηλή Κατανάλωση Ισχύος Και Υψηλές Επιδόσεις

“…To ergaleÐo èqei ulopoihjeÐ apì thn K. MÐtroglou[146] se sunergasÐa me to suggrafèa thc paroÔsac Didaktorik c Diatrib c. PTP KEF ALAIO 6. AXIOL OGHSH THS PROTEIN OMENHS MEJODOLOG IAS Ðnk TFTX epotelèsmt Ônjesh wondwn ulimkwsh pì t ergleÐ th Synopsis me teqnologik ilioj kh TSMC 0,13µm {m 1 , m 2 , .…”