An Accurate Drain Current Model of Monolayer Transition-Metal Dichalcogenide Tunnel FETs

Huh, In; Park, Sangchun; Shin, Mincheol; Choi, Woo Young

doi:10.1109/ted.2017.2716339

Cited by 6 publications

(3 citation statements)

References 38 publications

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“…8. Tins affect the channel screening length (ch) by adjusting the gate controllability [32], [33]. Larger Tins lowers the peak EY of TFETs because of ch increase, which decreases the peak electron energy, as shown in Figs.…”

Section: B Hci With the Variation Of Device Dimensionsmentioning

confidence: 98%

Quantitative Hot Carrier Injection Analysis of N-Type Tunnel Field-Effect Transistors

2023

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The hot carrier injection (HCI) of tunnel field-effect transistors (TFETs) is analyzed quantitatively under various conditions in terms of HCI-induced gate current (IG), HCI probability (IG/ID), potential energy, and lateral/vertical electric field for the first time. For example, the IG and IG/ID of TFETs are predicted in comparison with those of metal-oxide semiconductor FETs (MOSFETs) with the variation of gate voltage (VG), drain voltage (VD), gate insulator thickness (Tins), and channel length (Lch). According to the simulation results, TFETs show higher HCI probability than MOSFETs under the entire bias conditions because the former features strong peak lateral field at source-channel junction. For example, TFETs show ~1.8×10 2 x higher HCI current and ~5.9×10 6 x higher HCI probability than MOSFETs at VG = 4 V and VD = 3 V. The optimal HCI bias condition of TFETs is also analyzed.INDEX TERMS Tunnel field-effect transistors (TFETs), metal-oxide field-effect transistors (MOSFETs), hot carrier injection.

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Section: B Hci With the Variation Of Device Dimensionsmentioning

confidence: 98%

Quantitative Hot Carrier Injection Analysis of N-Type Tunnel Field-Effect Transistors

2023

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“…[6][7][8][9][10][11] Among these steep switching devices, the tunnel FET is a promising alternative to CMOS and has been studied extensively both experimentally [12][13][14][15][16][17][18][19][20][21] and theoretically. [22][23][24][25][26][27][28] Despite aiming for steep switching, most studies on TFETs face the challenge of TFETs not being steep due to the lack of on-current or high off-current. In terms of on-current, a direct bandgap III-V semiconductor with a light tunnel mass is a promising alternative.…”

Section: Introductionmentioning

confidence: 99%

Circuit speed oriented device design scheme for GaAsSb/InGaAs double-gate hetero-junction tunnel FETs

Fukuda

Nogami

Kunisada

et al. 2020

Jpn. J. Appl. Phys.

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This study investigated the device optimization scheme of a double-gate hetero-junction tunnel FET, which was expected to improve circuit performance. A thinner channel with a stronger electric field increases the tunnel on-current. Conversely, a thin channel results in a larger quantum sub-band energy and an effective bandgap, which decreases the tunnel on-current. Such tradeoffs are clarified by considering the quantum effects in a device simulation. Furthermore, the gate capacitance behavior, identified via device simulation, was considered, and it demonstrates that the double-gate hetero-junction tunnel FET has a substantial capacitance merit compared to CMOS transistors. The early stages of our work used the intrinsic delay for device optimization, as defined in the international technology roadmap for semiconductors. However, based on the comparison with the speed evaluation results of the ring oscillator, the device optimization scheme was improved. This was achieved by adopting a new effective delay index, based on the effective on-currents and effective gate capacitances. Studies on the CMOS device design also applied the concept of effective on-current; however, the design method presented herein is novel in that it introduced the concept of effective gate capacitance.

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“…[6][7][8][9][10][11] Among them, tunnel field-effect transistors (TFETs) have been most extensively studied, both experimentally [12][13][14][15][16][17][18][19][20] and theoretically. [21][22][23][24][25][26][27] Most of those TFETs were designed for realizing larger on-currents, smaller off-currents, and steep subthreshold slopes. On the other hand, short-channel effects (SCEs) of TFETs have not received sufficient attention, with only a few studies addressing this issue.…”

Section: Introductionmentioning

confidence: 99%

Simulation study of short-channel effects of tunnel field-effect transistors

Fukuda

Asai

Hattori

et al. 2018

Jpn. J. Appl. Phys.

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Short-channel effects of tunnel field-effect transistors (FETs) are investigated in detail using simulations of a nonlocal band-to-band tunneling model. Discussion is limited to silicon. Several simulation scenarios were considered to address different effects, such as source overlap and drain offset effects. Adopting the drain offset to suppress the drain leakage current suppressed the short channel effects. The physical mechanism underlying the short-channel behavior of the tunnel FETs (TFETs) was very different from that of metal–oxide–semiconductor FETs (MOSFETs). The minimal gate lengths that do not lose on-state current by one order are shown to be 3 nm for single-gate structures and 2 nm for double gate structures, as determined from the drain offset structure.

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An Accurate Drain Current Model of Monolayer Transition-Metal Dichalcogenide Tunnel FETs

Cited by 6 publications

References 38 publications

Quantitative Hot Carrier Injection Analysis of N-Type Tunnel Field-Effect Transistors

Quantitative Hot Carrier Injection Analysis of N-Type Tunnel Field-Effect Transistors

Circuit speed oriented device design scheme for GaAsSb/InGaAs double-gate hetero-junction tunnel FETs

Simulation study of short-channel effects of tunnel field-effect transistors

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