An 82%-efficient multiphase voltage-regulator 3D interposer with on-chip magnetic inductors

Tien, Kevin; Sturcken, Noah; Wang, Naigang; Nah, Jae-Woong; Dang, Bing; O’Sullivan, E. J.; Andry, Paul; Petracca, Michele; Carloni, Luca P.; Gallagher, W. J.; Shepard, Kenneth L.

doi:10.1109/vlsit.2015.7223648

Cited by 9 publications

(4 citation statements)

References 3 publications

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“…In particular, it supports the realization of fine-grained power management with multiple independent voltage/frequency domains. Thanks to the progress in developing integrated voltage regulators [1,7,29,30], each domain can correspond to an individual ESP tile, thus providing fine granularity both in time and space. Each regulator is managed through a dedicated controller for dynamic voltage-frequency scaling.…”

Section: A Scalable Architecturementioning

confidence: 99%

“…In particular, each accelerator may be activated by a software application only when it is necessary to execute its particular function. Thanks to new technologies for fine-grain dynamic power management [1,7,29,30], it is possible to power up only those SoC components needed to run the current workload. It is this ability of independent activation of selected specialized components that makes parallel heterogeneous architectures a value proposition to preserve the progress of the semiconductor industry in the so-called "age of dark silicon", when power limitations are stringent and homogeneous multicore scaling has hit diminished returns [13].…”

Section: Introductionmentioning

confidence: 99%

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Invited - The case for embedded scalable platforms

Carloni

2016

Proceedings of the 53rd Annual Design Automation Conference

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Heterogeneous system-on-chip (SoC) architectures are emerging as a fundamental computing platform across a variety of domains, from mobile to cloud computing. Heterogeneity, however, increases design complexity in terms of hardware-software interactions, access to shared resources, and diminished regularity of the design. Embedded Scalable Platforms are a novel approach to SoC design and programming that addresses these design-complexity challenges by combining an architecture and a methodology. The flexible socketed architecture simplifies the integration of heterogeneous components by balancing regularity and specialization. The companion methodology raises the level of abstraction to system-level design, thus promoting closer collaboration among software programmers and hardware engineers. The architecture is supported by a scalable communication infrastructure. The methodology leverages compositional design-space exploration with high-level synthesis. The case for Embedded Scalable Platforms is made based on experiments on the development of various full-system prototypes and experience in teaching these concepts in a new graduate course.

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Section: A Scalable Architecturementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Invited - The case for embedded scalable platforms

Carloni

2016

Proceedings of the 53rd Annual Design Automation Conference

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“…Request permissions from permissions@acm.org. come the focus of many research works [1,8,31,33] Typical IVRs are switching regulators that store energy in capacitors and/or inductors and deliver that energy at a potential controlled by a switching signal. Die-integrated switchedcapacitor regulators boast fast transient response, high peak efficiency (>90%), and minimal technology requirements.…”

Section: Introductionmentioning

confidence: 99%

“…However, they remain difficult to build into die-integrated systems due to the low quality factor and correspondingly low efficiency available in die-integrable inductor technologies [35]. Still, efficiency factors in the 70%-85% range have been reached with state-of-the-art inductor technology [14,31,33].…”

Section: Introductionmentioning

confidence: 99%

An FPGA-based infrastructure for fine-grained DVFS analysis in high-performance embedded systems

Mantovani

Cota

Tien

et al. 2016

Proceedings of the 53rd Annual Design Automation Conference

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Emerging technologies provide SoCs with fine-grained DVFS capabilities both in space (number of domains) and time (transients in the order of tens of nanoseconds). Analyzing these systems requires cycle-accurate accounting of rapidly-changing dynamics and complex interactions among accelerators, interconnect, memory, and OS. We present an FPGA-based infrastructure that facilitates such analyses for high-performance embedded systems. We show how our infrastructure can be used to first generate SoCs with looselycoupled accelerators, and then perform design-space exploration considering several DVFS policies under full-system workload scenarios, sweeping spatial and temporal domain granularity.

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A fully integrated soft switched high frequency resonant DC‐DC voltage regulator

Meshkat

Dehghani

Farzanehfard

2022

Circuit Theory & Apps

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Fully integrated 750-MHz resonant voltage regulator is presented. Providing soft switching conditions for the transistors has prevented degradation of the converter efficiency at this high switching frequency. High switching frequency has reduced volume of the passive on-chip components and thus increased the converter current density. Due to the limitations of the CMOS processes, control and gate drive circuits are designed to increase chip reliability. One of the major challenges of the fully integrated voltage regulators is the on-chip inductor realization. Based on the mathematical models for inductance and resistance of spiral on-chip inductor, the geometric dimensions of the employed inductor are optimally designed to have maximum quality factor and minimum chip area. The power switches are optimized to achieve maximum efficiency. All post layout parasitic elements of MOSFETs and metal routings including inductive effects are extracted using 3-D EM simulation and finite element method for 0.18-μm standard CMOS technology. Maximum output voltage ripple is 5.2% at maximum load current. Peak efficiency of the proposed on-chip power supply is 82% when input/output voltage is 1.8 V/1.48 V and load current is 120 mA. Maximum value of the efficiency enhancement factor is 42% for output input/voltage of 1.8 V/0.55 V. Current density of the proposed converter is 574 mA/mm 2 . In the worst case, the load step causes an overvoltage/undervoltage smaller than 15.56% at the output voltage. K E Y W O R D Sfully integrated voltage regulator (FIVR), soft switching, resonant DC-DC buck converter, high current density, on-chip inductor optimum design

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An 82%-efficient multiphase voltage-regulator 3D interposer with on-chip magnetic inductors

Cited by 9 publications

References 3 publications

Invited - The case for embedded scalable platforms

Invited - The case for embedded scalable platforms

An FPGA-based infrastructure for fine-grained DVFS analysis in high-performance embedded systems

A fully integrated soft switched high frequency resonant DC‐DC voltage regulator

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