An FPGA-based infrastructure for fine-grained DVFS analysis in high-performance embedded systems

Mantovani, Paolo; Cota, Emilio G.; Tien, Kevin; Pilato, Christian; Guglielmo, Giuseppe Di; Shepard, Ken; Carloni, Luca P.

doi:10.1145/2897937.2897984

Cited by 31 publications

(36 citation statements)

References 41 publications

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“…There are two well-established methods to save on energy in embedded devices, and they are dynamic voltage and frequency scaling (DVFS) [16] and the RTH mechanism [10]. Integrated circuits are recently equipped with a number of sleep-state features.…”

Section: Literature Review 21 Previous Related Workmentioning

confidence: 99%

Optimizing FPGA-based CNN accelerator for energy efficiency with an extended Roofline model

Ayat¹,

Khalil-Hani²,

Rahman³

2018

Turk J Elec Eng & Comp Sci

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Abstract:In recent years, the convolutional neural network (CNN) has found wide acceptance in solving practical computer vision and image recognition problems. Also recently, due to its flexibility, faster development time, and energy efficiency, the field-programmable gate array (FPGA) has become an attractive solution to exploit the inherent parallelism in the feedforward process of the CNN. However, to meet the demands for high accuracy of today's practical recognition applications that typically have massive datasets, the sizes of CNNs have to be larger and deeper. Enlargement of the CNN aggravates the problem of off-chip memory bottleneck in the FPGA platform since there is not enough space to save large datasets on-chip. In this work, we propose a memory system architecture that best matches the off-chip memory traffic with the optimum throughput of the computation engine, while it operates at the maximum allowable frequency. With the help of an extended version of the Roofline model proposed in this work, we can estimate memory bandwidth utilization of the system at different operating frequencies since the proposed model considers operating frequency in addition to bandwidth utilization and throughput. In order to find the optimal solution that has the best energy efficiency, we make a trade-off between energy efficiency and computational throughput. This solution saves 18% of energy utilization with the trade-off having less than 2% reduction in throughput performance. We also propose to use a race-to-halt strategy to further improve the energy efficiency of the designed CNN accelerator. Experimental results show that our CNN accelerator can achieve a peak performance of 52.11 GFLOPS and energy efficiency of 10.02 GFLOPS/W on a ZYNQ ZC706 FPGA board running at 250 MHz, which outperforms most previous approaches.

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Section: Literature Review 21 Previous Related Workmentioning

confidence: 99%

Optimizing FPGA-based CNN accelerator for energy efficiency with an extended Roofline model

Ayat¹,

Khalil-Hani²,

Rahman³

2018

Turk J Elec Eng & Comp Sci

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“…To adhere to the application hardware requirements, much prior research focused on configurable hardware (e.g., [13][14][15][16][17][18][19][20][21][22][23]), configurable caches (e.g., [3,4,[24][25][26][27]), and design space exploration (e.g., [5][6][7][9][10][11][28][29][30][31][32]). Given this expansive prior work, we discuss fundamentals of configurable hardware, followed by specific related work in configurable caches and design space exploration with fundamentals that are directly applicable to our approach.…”

Section: Related Workmentioning

confidence: 99%

“…Previous works have explored DFVS [15] as a solution to save energy, included DVFS as part of online and offline scheduling algorithms [17], increased the DVFS efficiency by allowing different units inside a CPU to operate at different voltage-frequencies [2], enabled a group of components to operate at a different voltage-frequency [18,19], leveraged DVFS to reduce idle energy [20], or evaluated the tradeoff between the discrete values of DVFS and energy savings [21,23]. Whereas these works contributed novel hardware architectures using DVFS, we plan to include DVFS configurations (e.g., as in Reference [19,21]) in our design space in future works.…”

Section: Configurable Hardwarementioning

confidence: 99%

Low Effort Design Space Exploration Methodology for Configurable Caches

Alsafrjalani

Gordon‐Ross

2018

Computers

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Designers can reduce design space exploration time and efforts using the design space subsetting method that removes energy-redundant configurations. However, the subsetting method requires a priori knowledge of all applications. We analyze the impact of a priori application knowledge on the subset quality by varying the amount of a priori application information available to designers during design time from no information to a general knowledge of the application domain. The results showed that only a small set of applications representative of the anticipated applications' general domains alleviated the design efforts and was sufficient to provide energy savings within 5.6% of the complete, unsubsetted design space. Furthermore, since using a small set of applications was likely to reduce the design space exploration time, we analyze and quantify the impact of a priori applications knowledge on the speedup in the execution time to select the desired configurations. The results revealed that a basic knowledge of the anticipated applications reduced the subset design space exploration time by up to 6.6X.

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“…An infrastructure has been proposed for fine-grained DVFS of FPGA-implemented SoCs [11]. DVFS was combined with task mapping by Wu et al, with tasks optimally executed on CPU, GPU or FPGA cores dependent on a realtime power budget [12].…”

Section: Background and Related Workmentioning

confidence: 99%

KOCL: Power Self- Awareness for Arbitrary FPGA-SoC-Accelerated OpenCL Applications

et al. 2017

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Abstract-Given the need for developers to rapidly produce complex, high-performance and energy-efficient hardware systems, methods facilitating their intelligent runtime management are of ever-increasing importance. For energy optimisation, such control decisions require knowledge of power usage at subsystem granularity. This information must be made accessible to developers accustomed to creating systems from high-level descriptions, including those written in OpenCL. This article introduces KOCL: a tool allowing OpenCL developers targetting FPGA-SoC devices to query live kernel-level power consumption using function calls embedded in their host code. To maximise accessibility, KOCL is incredibly easy to use; crucially, it requires zero exposure to hardware.

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An FPGA-based infrastructure for fine-grained DVFS analysis in high-performance embedded systems

Cited by 31 publications

References 41 publications

Optimizing FPGA-based CNN accelerator for energy efficiency with an extended Roofline model

Optimizing FPGA-based CNN accelerator for energy efficiency with an extended Roofline model

Low Effort Design Space Exploration Methodology for Configurable Caches

KOCL: Power Self- Awareness for Arbitrary FPGA-SoC-Accelerated OpenCL Applications

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