An 82&amp;#x03BC;A/MHz microcontroller with embedded FeRAM for energy-harvesting applications

Zwerg, Michael; Baumann, A.; Kuhn, R.; Arnold, Matthias; Nerlich, Ronald; Herzog, Marcus; Ledwa, Ralph; Sichert, C.; Rzehak, Volker; Thanigai, Priya; Eversmann, B.

doi:10.1109/isscc.2011.5746342

Cited by 66 publications

(40 citation statements)

References 5 publications

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“…This is the case with modern microcontrollers, e.g. [6]. It also requires enough energy to be stored in the capacitance between the supply rails to save a full snapshot.…”

Section: Hibernusmentioning

confidence: 99%

“…The test platform (Fig. 3) uses a development board combining a Texas Instruments MSP430 processor [6] with FRAM. This means that its decoupling capacitance alone allows E δ >> E σ when V = V max , requiring no additional energy storage (battery or large capacitor) to support Hibernus.…”

Section: A Implementing Hibernusmentioning

confidence: 99%

“…This brief proposes Hibernus 1 , a new approach which automatically saves a snapshot only once (without the need for checkpoint placement heuristics), immediately before power failure, then sleeps. Hibernus saves the system's complete volatile memory; this is enabled in part by developments in Ferroelectric RAM (FRAM), a NVM technology that is more efficient than flash, and is now being monolithically integrated into low-power microcontrollers [6]. The speed and efficiency of integrated FRAM means we can react to power loss and save a snapshot using only the energy stored in a system's decoupling capacitance.…”

Section: Introductionmentioning

confidence: 99%

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Hibernus: Sustaining Computation During Intermittent Supply for Energy-Harvesting Systems

Balsamo

Weddell

Merrett

et al. 2015

IEEE Embedded Syst. Lett.

220

297

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Abstract-A key challenge to the future of energy-harvesting systems is the discontinuous power supply that is often generated. We propose a new approach, Hibernus, which enables computation to be sustained during intermittent supply. The approach has a low energy and time overhead which is achieved by reactively hibernating: saving system state only once, when power is about to be lost, and then sleeping until the supply recovers. We validate the approach experimentally on a processor with FRAM nonvolatile memory, allowing it to reactively hibernate using only energy stored in its decoupling capacitance. When compared to a recently proposed technique, the approach reduces processor time and energy overheads by 76-100% and 49-79% respectively.

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“…This is the case with modern microcontrollers, e.g. [6]. It also requires enough energy to be stored in the capacitance between the supply rails to save a full snapshot.…”

Section: Hibernusmentioning

confidence: 99%

Section: A Implementing Hibernusmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Hibernus: Sustaining Computation During Intermittent Supply for Energy-Harvesting Systems

Balsamo

Weddell

Merrett

et al. 2015

IEEE Embedded Syst. Lett.

220

297

View full text Add to dashboard Cite

show abstract

“…Nonvolatile processing-continuously operating a digital circuit and retaining state through frequent power interruptions-creates new applications for portable electronics operating from harvested energy [1] and high-performance systems managing power by operating "normally off" [2,3]. To enable these scenarios, energy processing must happen in parallel with information processing.…”

Section: Introductionmentioning

confidence: 99%

A 3.4-pJ FeRAM-Enabled D Flip-Flop in 0.13-$\mu \hbox{m}$ CMOS for Nonvolatile Processing in Digital Systems

Qazi

Amerasekera

Chandrakasan

2014

IEEE J. Solid-State Circuits

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In order to realize a digital system with no distinction between "on" and "off," computational state must be stored in non-volatile memory elements. If the energy cost and time cost of managing computational state in nonvolatile memory can be lowered to the microsecond and picojoule per bit level, such a system could operate from unreliable harvested energy, never requiring a reboot. This work presents a nonvolatile D flip-flop (NVDFF) designed in 0.13 µm CMOS that retains state in ferroelectric capacitors during sporadic power loss. The NVDFF is integrated into an ASIC design flow, and a test-case nonvolatile FIR filter with an accompanying power management unit automatically saves and restores state based on the status of a one-bit indicator of energy availability. Correct operation has been verified over power cycle intervals from 4.8 µs to 1 day. The round-trip save-restore energy is 3.4 pJ per NVDFF. Also presented are statistical measurements across 21,000 NVDFFs to validate the capability of the circuit to achieve the requisite 10 ppm failure rate for embedded system applications.

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…”

mentioning

confidence: 99%

A 3.4pJ FeRAM-enabled D flip-flop in 0.13µm CMOS for nonvolatile processing in digital systems

Qazi¹,

Amerasekera²,

Chandrakasan³

2013

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers

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TXNonvolatile processing-continuously operating a digital circuit and retaining state through frequent power interruptions-creates new applications for portable electronics operating from harvested energy [1] and high-performance systems managing power by operating "normally off" [2]. To enable these scenarios, energy processing must happen in parallel with information processing. This work makes the following contributions: 1) the design of a nonvolatile D flip-flop (NVDFF) with embedded ferroelectric capacitors (fecaps) that senses data robustly and avoids race conditions; 2) the integration of the NVDFF into the ASIC design flow with a power management unit (PMU) and a simple one-bit interface to brown-out detection circuitry; and 3) a characterization of the NVDFF statistical signal margin and the energy cost of retaining data. This chip's process technology features embedded ferroelectric capacitors that store data in a charge versus bias voltage hysteresis [3]. This hysteresis is shown in Fig. 1 along with the principle of self-timed sensing. Prior to sensing, the fecaps have been programmed to opposite data states, corresponding to opposite points on the zero bias voltage points of the hysteresis curve. Identical charging currents integrate the difference in remnant charge between the two fecaps onto nodes FET and FEC. The node to first cross the diode voltage drop plus a PMOS threshold will quickly pull the internal node of the sensing latch high. The ferroelectric capacitance is large compared to the internal node of the sensing latch, so a small voltage difference on the high capacitance nodes FET and FEC is converted to a large voltage difference on the latch nodes. In addition to being self-timed, this approach develops sufficient bias (1.1 V) before the fecaps are sensed. Fecap signal dynamics are exponentially sensitive to voltage bias [4], so it is important to avoid the performance penalty associated with sensing at low bias.The schematic of the nonvolatile latch in Fig. 2 shows the additional transistors for saving data, isolating fecaps during active operation, and protecting fecaps during power loss. This latch is combined as the slave stage with a clocked CMOS master latch to form the NVDFF in Fig. 3. The waveforms show how the ports PG, LD, EQ, and VDDNV need to be sequenced during power interruption. While active, PG=LD=0, and nodes FET and FEC act as a virtual supply for the slave latch. The save operation initiates when PG rises as CK is held low, cutting off VDDNV and enabling a weak pull-down path (M8-M10) to discharge one of the two fecaps (write "0") depending on the data state of the slave latch. The subsequent rise of LD preserves the data in the other fecap, which has already been written to a "1" during the previous restore operation. Prior to power loss, the EQ signal assertion clears floating voltages inside the slave latch, and then the VDDNV rail is discharged to prevent conducting paths to nodes FET/FEC. A complementary sequence is applied after VDD and VDDNV return high for ...

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An 82μA/MHz microcontroller with embedded FeRAM for energy-harvesting applications

Cited by 66 publications

References 5 publications

Hibernus: Sustaining Computation During Intermittent Supply for Energy-Harvesting Systems

Hibernus: Sustaining Computation During Intermittent Supply for Energy-Harvesting Systems

A 3.4-pJ FeRAM-Enabled D Flip-Flop in 0.13-$\mu \hbox{m}$ CMOS for Nonvolatile Processing in Digital Systems

A 3.4pJ FeRAM-enabled D flip-flop in 0.13µm CMOS for nonvolatile processing in digital systems

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An 82&#x03BC;A/MHz microcontroller with embedded FeRAM for energy-harvesting applications

Cited by 66 publications

References 5 publications

Hibernus: Sustaining Computation During Intermittent Supply for Energy-Harvesting Systems

Hibernus: Sustaining Computation During Intermittent Supply for Energy-Harvesting Systems

A 3.4-pJ FeRAM-Enabled D Flip-Flop in 0.13-$\mu \hbox{m}$ CMOS for Nonvolatile Processing in Digital Systems

A 3.4pJ FeRAM-enabled D flip-flop in 0.13&#x00B5;m CMOS for nonvolatile processing in digital systems

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Product

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An 82μA/MHz microcontroller with embedded FeRAM for energy-harvesting applications

A 3.4pJ FeRAM-enabled D flip-flop in 0.13µm CMOS for nonvolatile processing in digital systems