A 3.4-pJ FeRAM-Enabled D Flip-Flop in 0.13-$\mu \hbox{m}$ CMOS for Nonvolatile Processing in Digital Systems

Abstract

In order to realize a digital system with no distinction between "on" and "off," computational state must be stored in non-volatile memory elements. If the energy cost and time cost of managing computational state in nonvolatile memory can be lowered to the microsecond and picojoule per bit level, such a system could operate from unreliable harvested energy, never requiring a reboot. This work presents a nonvolatile D flip-flop (NVDFF) designed in 0.13 µm CMOS that retains state in ferroelectric capacitors during sporadic power loss. The NVDFF is integrated into an ASIC design flow, and a test-case nonvolatile FIR filter with an accompanying power management unit automatically saves and restores state based on the status of a one-bit indicator of energy availability. Correct operation has been verified over power cycle intervals from 4.8 µs to 1 day. The round-trip save-restore energy is 3.4 pJ per NVDFF. Also presented are statistical measurements across 21,000 NVDFFs to validate the capability of the circuit to achieve the requisite 10 ppm failure rate for embedded system applications.

Hibernus++: A Self-Calibrating and Adaptive System for Transiently-Powered Embedded Devices

“…This limits its applicability to purely computational applications, rather than embedded systems which may need to interface with other devices. A few recently published papers show that the time and energy cost of distributed state-retentive logic elements can be lowered by orders of magnitude with respect to traditional flash-based approaches using alternative technology such as FRAM [21] and ReRAM [22].…”

Total ionizing dose sensitivity of function blocks in FRAM

“…Hence, more and more attention has been focused on the potential use of FRAMs for space and low-power applications because of these advantages [9][10][11][12]. FRAMs also can be easily embedded with other CMOS circuits to offer system-on-a-chip (SoC) solutions [13,14], which can help reducing the cost and size of the space and consumer electronic systems.…”

A compact low-power nonvolatile flip-flop using domain-wall-motion-device-based single-ended structure

“…The combination of nonvolatile logic circuits together with a power-gating technique where power supply of all the idle function blocks are temporally turned off, is one promising solution for the standby power problem in nanoscale CMOS technologies [1,2,3]. A nonvolatile flip-flop (NV-FF) [1,3,4,5,6] is an essential component for a nonvolatile logic LSI since temporal data of each function block must be clock-synchronized and retained during poweroff.…”

“…A nonvolatile flip-flop (NV-FF) [1,3,4,5,6] is an essential component for a nonvolatile logic LSI since temporal data of each function block must be clock-synchronized and retained during poweroff. Because temporal data in an NV-FF must be stored in a nonvolatile device every time before power-off, it is very important that the nonvolatile device has unlimited endurance as well as fast switching capability in nanoseconds.…”