An 8 bit 150 MHz CMOS D/A converter with 2 Vp-p wide range output

Kumazawa, N.; Fukushima, N.; Sakamoto, Noriaki

doi:10.1109/vlsic.1990.111092

Cited by 5 publications

(2 citation statements)

References 1 publication

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“…Recently, many high-speed CMOS DAC's have been designed using either weighted current array [1]- [4] or current cell matrix [5]- [7]. These current-switching DAC's allow fast and accurate settling.…”

Section: Introductionmentioning

confidence: 99%

A 10-b 125-MHz CMOS digital-to-analog converter (DAC) with threshold-voltage compensated current sources

Chin

1994

IEEE J. Solid-State Circuits

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This paper describes a 10-b high-speed COMS DAC fabricated by 0.8-pm double-poly double-metal CMOS technology. In the DAC, a new current source called the thresholdvoltage compensated current source is used in the two-stage current array to reduce the linearity error caused by inevitable current variations of the current sources. In the two-stage weighted current array, only 32 master and 32 slave unit current sources are required. Thus silicon area and stray capacitance can be reduced significantly. Experimental results show that a conversion rate of 125 MHz is achievable with differential and integral linearity errors of 0.21 LSB and 0.23 LSB, respectively. The power consumption is 150 mW for a single 5-V power supply. The ridfall time is 3 ns and the full-scale settling time to *1/2 LSB is within 8 ns. The chip area is 1.8 mm x 1.0 mm.

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Section: Introductionmentioning

confidence: 99%

A 10-b 125-MHz CMOS digital-to-analog converter (DAC) with threshold-voltage compensated current sources

Chin

1994

IEEE J. Solid-State Circuits

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“…1 to 5 shows the block diagrams of the products [3] shown in table 1. Recently, we have CMOS AD/DAC cells in our CMOS cell library because of the improvement of the conversion speed and resolution [4,5]. Table 2 shows our CMOS AD/DAC cell library.…”

Section: Sony Mixed Signal Devicesmentioning

confidence: 99%