An 182mW 1-60Gb/s Configurable PAM-4/NRZ Transceiver for Large Scale ASIC Integration in 7nm FinFET Technology

Kocaman, Namik; Singh, Ullas; Raghavan, Bharath; Lyer, Arvindh; Thasari, Kumar; Surana, Saurabh; Jung, Jun Won; Jeong, Jae−Hun; Zhang, Heng; Vasani, Anand; Shim, Yoon‐Bo; Huang, Zhi; Garg, Anubhav; Lee, Hsiang-bin; Wu, Bo; Liu, Feifei; Wang, Ray; Loh, Matthew; Wang, Alex; Caresosa, M.; Zhang, Bo; Momtaz, Afshin

doi:10.1109/isscc42614.2022.9731688

Cited by 12 publications

(2 citation statements)

References 2 publications

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“…The data-traffic explosion driven by cloud computing, 5G networks, industrial IoT, and virtual reality has accelerated the demand for high-speed SerDes transceivers to provide massive data throughput [1,2,3,4,5,6,7,8]. Previous studies have demonstrated that four-level pulse amplitude modulation (PAM-4) is superior to non-return-to-zero (NRZ) for the 56∼112-Gb/s serial data communications due to its doubled spectral efficiency, halved Nyquist frequency, and relaxed clock speeds [9,10,11,12,13,14,15].…”

Section: Introductionmentioning

confidence: 99%

A high-output-swing 64-Gb/s PAM-4 transmitter with a 4-tap hybrid FFE in 28-nm CMOS

Xu,

Zheng,

Wang

et al. 2024

IEICE Electron. Express

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This article presents a high-output-swing 64-Gb/s four-level pulse amplitude modulation (PAM-4) transmitter, in which a 4-tap hybrid feed-forward equalizer (FFE) employing both fractionally-spaced preemphasis (FS-PE) and baud-spaced de-emphasis (BS-DE) is proposed. The PE technique enlarges the output swing by directly stacking pre-distortion pulses, and naturally consumes less power as it boosts only the desired symbols. The FS-based pre/post1 taps equalize the high-frequency loss, provide a wide compensation range beyond the Nyquist frequency, and realize a flexible equalization capability, while the BS-DE-based post2 tap compensates for the low-frequency channel loss. Fabricated in a 28-nm CMOS process, the 64-Gb/s transmitter obtains a differential output swing of 1.4 V ppd with an energy efficiency of 1.53 pJ/bit.

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Section: Introductionmentioning

confidence: 99%

A high-output-swing 64-Gb/s PAM-4 transmitter with a 4-tap hybrid FFE in 28-nm CMOS

Xu,

Zheng,

Wang

et al. 2024

IEICE Electron. Express

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show abstract

“…The necessity of 2× more samples per unit interval (UI) in ! !CDRs doubles the number of PIs and sampling clock phases compared to BRCDRs [2], [5]- [10]. Therefore, most clock recoveries in high-speed RXs rely on BRPDs for better energy efficiency [11]- [14].…”

Section: Introductionmentioning

confidence: 99%

A 4×32 Gb/s 1.8 pJ/bit Collaborative Baud-Rate CDR with Background Eye-Climbing Algorithm and Low-Power Global Clock Distribution

Kim,

Park,

Shin

et al. 2024

Preprint

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This paper presents design techniques for an energyefficient multi-lane receiver (RX) with baud-rate clock and data recovery (CDR), which is essential for high-throughput lowlatency communication in high-performance computing systems. The proposed low-power global clock distribution not only significantly reduces power consumption across multi-lane RXs but is capable of compensating for the frequency offset without any phase interpolators. To this end, a fractional divider controlled by CDR is placed close to the global phase locked loop. Moreover, in order to address the sub-optimal lock point of conventional baudrate phase detectors, the proposed CDR employs a background eye-climbing algorithm, which optimizes the sampling phase and maximizes the vertical eye margin (VEM). Fabricated in a 28 nm CMOS process, the proposed 4×32 Gb/s RX shows a low integrated fractional spur of -40.4 dBc at a 2500 ppm frequency offset. Furthermore, it improves bit-error-rate performance by increasing the VEM by 17 %. The entire RX achieves the energy efficiency of 1.8 pJ/bit with the aggregate data rate of 128 Gb/s.

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A 135 GHz Direct-Digital 16-QAM Wireless and DWG Link

D’heer,

Reynaert

2024

Analog Circuits and Signal Processing

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An 182mW 1-60Gb/s Configurable PAM-4/NRZ Transceiver for Large Scale ASIC Integration in 7nm FinFET Technology

Cited by 12 publications

References 2 publications

A high-output-swing 64-Gb/s PAM-4 transmitter with a 4-tap hybrid FFE in 28-nm CMOS

A high-output-swing 64-Gb/s PAM-4 transmitter with a 4-tap hybrid FFE in 28-nm CMOS

A 4×32 Gb/s 1.8 pJ/bit Collaborative Baud-Rate CDR with Background Eye-Climbing Algorithm and Low-Power Global Clock Distribution

A 135 GHz Direct-Digital 16-QAM Wireless and DWG Link

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