An 11-Bit Single-Ended SAR ADC with an Inverter-Based Comparator for Design Automation

Abstract

This paper proposes a low power single-ended successive approximation register (SAR) analog-to-digital converter (ADC) to replace the only analog active circuit, the comparator, with a digital circuit, which is an inverter-based comparator. The replacement helps possible design automation. The inverter threshold voltage variation impact is minimal because an SAR ADC has only one comparator, and many applications are either insensitive to the resulting ADC offset or easily corrected digitally. The proposed resetting approach mitigates leakage when the input is close to the threshold voltage. As an intrinsic headroom-free, and thus low-rail-voltage, friendly structure, an inverter-based comparator also occupies a small area. Furthermore, an 11-bit ADC was designed and manufactured through a 0.35-μm CMOS process by adopting a low-power switching procedure. The ADC achieves an FOM of 181 fJ/Conv.-step at a 25 kS/s sampling rate when the supply voltage V DD is 1.2 V. key words: Analog-to-digital converter, successive approximation register ADC, inverter-based, design automation.

High resolution mutated dynamic precision power gated comparator for 9-bit SAR ADC

“…Design and implementation of a low-power 1V, 77.26μW 6-bit SAR ADC in Cadence 90nm CMOS process for biomedical application is depicted in [7]. The proposed comparator consumes low power with the medium speed in the SAR ADCs.…”

“…To achieve higher gain W/L should be decreased, hence |VGS -VTP| need to be increased and lower the common-mode voltage at the output nodes. M5 and M6 are included to improve current in M1 and M2 so that the gain increases at the square root of the difference of current in M1 and M2 given as in Equation (7).…”