A 6-bit 4 MS/s, V CM -based sub-radix-2 SAR ADC with inverter type comparator

Rikan, Behnam Samadpoor; Lee, Dong‐Soo; Lee, Kang-Yoon

doi:10.1016/j.mejo.2017.02.009

Cited by 11 publications

(7 citation statements)

References 16 publications

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“…This causes a reduction in the switching power. For one period of a sine wave signal in V CM ‐based structure, there is switching in 100% of the capacitors . However, in this proposed switching, for one period of a sine wave, there is switching in about 40% of the total capacitors on average.…”

Section: Architecture Of the Proposed Adc And Switching Schemementioning

confidence: 90%

“…For one period of a sine wave signal in V CM -based structure, there is switching in 100% of the capacitors. 8,9 However, in this proposed switching, for one period of a sine wave, there is switching in about 40% of the total capacitors on average. Also, the unit capacitor sizes are half of the one in V CM -based structure.…”

Section: Switching Scheme Of the Segmented Sar Adcmentioning

confidence: 99%

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A 6‐bit 4 MS/s 26fJ/conversion‐step segmented SAR ADC with reduced switching energy for BLE

Rikan

Abbasizadeh

Cho

et al. 2017

Circuit Theory & Apps

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Summary This paper presents a 6‐bit 4 MS/s segmented successive approximation register analog‐to‐digital converter for Bluetooth low energy transceiver applications. To improve the linearity and reduce the switching power consumption, a segmented structure with new switching scheme is adopted in the capacitive digital‐to‐analog converter. The proposed switching sequence determines the MSBs according to the thermometer codes and skips some of the unnecessary steps while avoiding bubble errors. To ensure the common mode voltage remains comparatively steady, and to avoid employing power‐hungry common mode reference voltage circuits, each capacitor is divided into 2 identical small capacitors, connecting one of them to “high” and the other one to “low”. The switching sequence is straightforward, and a split capacitor with an integer value is applied, which almost halves the total number of capacitors while retaining the unit capacitor value intact. The prototype analog‐to‐digital converter is fabricated and measured in a 55‐nm (shrinked 65 nm) complementary metal‐oxide semiconductor process and achieves 5.48 to 5.92 Effective Number of Bits (ENOB) at a sampling frequency of 4 MS/s. The Signal to Noise and Distortion Ratio (SNDR) and Spurious Free Dynamic Range (SFDR) for Nyquist input frequency are 34.79 and 40.03 dB, respectively. The current consumption is 4.8 μA from a 1.0‐V supply, which corresponds to the figure of merit of 26 fJ/conversion‐step. The total active area of the analog‐to‐digital converters for the I and Q paths of the receiver is 105 μm × 140 μm.

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Section: Architecture Of the Proposed Adc And Switching Schemementioning

confidence: 90%

Section: Switching Scheme Of the Segmented Sar Adcmentioning

confidence: 99%

A 6‐bit 4 MS/s 26fJ/conversion‐step segmented SAR ADC with reduced switching energy for BLE

Rikan

Abbasizadeh

Cho

et al. 2017

Circuit Theory & Apps

Self Cite

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“…With this capacitor size, and according to the Refs. [3] and [16], the noise power due to the sampling [kT/C] in the CDAC is almost P ns = 2.58 × 10 −9 [V 2 ]. In addition, considering the full-scale sinusoid, the maximum input signal power is 1.62 [V 2 ].…”

Section: Error Correction Capacitor Bank Mismatch and Noise Considermentioning

confidence: 99%

“…Nevertheless, as the resolution of these structures increases, the number of the capacitors in the capacitor DAC (CDAC) also increases, which makes the structure bulky [1,2]. In addition, the mismatch in the CDAC degrades the performance of these structures [3][4][5]. To solve the mismatch issue in the CDAC, the unit capacitor sizes should be increased.…”

Section: Introductionmentioning

confidence: 99%

A 10- and 12-Bit Multi-Channel Hybrid Type Successive Approximation Register Analog-to-Digital Converter for Wireless Power Transfer System

et al. 2018

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This paper presents a successive approximation register (SAR) analog-to-digital converter (ADC) designed for a wireless power transfer system. This is a four–channel SAR ADC structure with 10-bit resolution for each channel, which can also be applied as a single 12-bit ADC. To reduce the area and the number of the required devices in the ADC module, a hybrid-type structure with capacitor and resistor DACs is applied, in which the resistor DAC is shared between channels and determines the seven least significant bits (LSB)s, while the capacitor DAC determines the three most significant bits (MSBs). For the 12-bit operation mode, and to reduce the number of capacitors required in the capacitor DAC, the capacitors of the four channels are shared to determine the five MSBs. A foreground calibration is applied to the capacitor DAC to remedy the gain and offset errors after fabrication. An additional low resistive path is also implemented in the resistor DAC for error correction. The conversion speed for 10- and 12-bit operations reaches up to 1 and 0.5 MS/s, respectively. The prototype ADC is designed in a 180 nm complementary metal-oxide semiconductor (CMOS) process. For 10- and 12-bit operating modes, this ADC module achieves up to 9.71 and 11.76 effective number of bits (ENOBs), respectively.

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“…The Successive Approximation Register (SAR) ADC as a candidate is reported as the most power efficient ADC structure. Nevertheless, as the resolution of the SAR ADCs are increased, these structures become bulky and the mismatch problem in the DAC would be more serious [5,6,7].…”

Section: Introductionmentioning

confidence: 99%

A Sigma-Delta ADC for Signal Conditioning IC of Automotive Piezo-Resistive Pressure Sensors with over 80 dB SNR

Rikan

Kim

Ahmad

et al. 2018

Sensors

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This paper presents a second-order discrete-time Sigma-Delta (SD) Analog-to-Digital Converter (ADC) with over 80 dB Signal to Noise Ratio (SNR), which is applied in a signal conditioning IC for automotive piezo-resistive pressure sensors. To reduce the flicker noise of the structure, choppers are used in every stage of the high gain amplifiers. Besides, to reduce the required area and power, only the CIC filter structure is adopted as a decimation filter. This filter has a configurable structure that can be applied to different data rates and input signal bandwidths. The proposed ADC was fabricated and measured in a 0.18-µm CMOS process. Due to the application of only a CIC filter, the total active area of the SD-ADC and reference generator is 0.49 mm2 where the area of the decimation filter is only 0.075 mm2. For the input signal bandwidth of 1.22 kHz, it achieved over 80 dB SNR in a 2.5 MHz sampling frequency while consuming 646 µW power.

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A 6-bit 4 MS/s, V CM -based sub-radix-2 SAR ADC with inverter type comparator

Cited by 11 publications

References 16 publications

A 6‐bit 4 MS/s 26fJ/conversion‐step segmented SAR ADC with reduced switching energy for BLE

A 6‐bit 4 MS/s 26fJ/conversion‐step segmented SAR ADC with reduced switching energy for BLE

A 10- and 12-Bit Multi-Channel Hybrid Type Successive Approximation Register Analog-to-Digital Converter for Wireless Power Transfer System

A Sigma-Delta ADC for Signal Conditioning IC of Automotive Piezo-Resistive Pressure Sensors with over 80 dB SNR

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