An 0.8&amp;amp;#181;m CMOS technology for high performance logic applications

Chapman, R. A.; Haken, R.A.; Bell, David A.; Wei, C.C.; Havemann, R.H.; Tang, Tony; Holloway, T.C.; Gale, R.J.

doi:10.1109/iedm.1987.191432

Cited by 23 publications

(5 citation statements)

References 2 publications

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“…Applications for tin oxide films range from use as a transparent electrode in photovoltaic cells, imaging and display devices to use as an energy conserving coating on windows and lightbulbs. Work on transparent, conductive coatings has been reviewed (1,2). The preparation and physical properties of tin oxide materials also have been reviewed (3).…”

Section: Discussionmentioning

confidence: 99%

“…The breakdown voltages for the 0.8 ~m devices are expected to be lower because of the thinner oxide, but these values are considered satisfactory in that all structures exhibit Vbds higher than minimum acceptable breakdown for a poly block capacitor given in Eq. [1]. In this equation, Tax is the oxide thickness in nm Acceptable Vbd = 8.0V + 0.3 (Tax) [1] Figure 7 shows a histogram of breakdown voltage distribution for poly block over n-well block capacitors on one n+-p diode leakage studies on 1.0 ~m CMOS wafers utilized rectangular n + structures defined on the p-well with areas of 244, 384, and 664 ~m 2. p+-n structures were fabricated in n-well in a similar fashion but with opposite conductivity type.…”

Section: Electrical Characterizationmentioning

confidence: 99%

“…[1]. In this equation, Tax is the oxide thickness in nm Acceptable Vbd = 8.0V + 0.3 (Tax) [1] Figure 7 shows a histogram of breakdown voltage distribution for poly block over n-well block capacitors on one n+-p diode leakage studies on 1.0 ~m CMOS wafers utilized rectangular n + structures defined on the p-well with areas of 244, 384, and 664 ~m 2. p+-n structures were fabricated in n-well in a similar fashion but with opposite conductivity type. Leakage currents were comparable on PBL and conventional LOCOS split lots, as summarized in Table IV.…”

Section: Electrical Characterizationmentioning

confidence: 99%

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Characterization of Poly‐Buffered LOCOS in Manufacturing Environment

Guldi

McKee

Damminga

et al. 1989

J. Electrochem. Soc.

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Poly‐buffered LOCOS (1–4) is an advanced, electrical isolation scheme developed as an alternative to conventional LOCOS (5–7) to minimize field oxide encroachment into active regions while maintaining satisfactory field thresholds with designs employing 1.0 μm active regions and 1.2 μm isolation spacings. Poly‐buffered LOCOS, or PBL, facilitates design rule shrinking and smaller cell size required for future technologies such as EPIC‐2 (1). This isolation scheme utilizes an oxide/poly/nitride sandwich to block field oxidation in active regions instead of the oxide/nitride sandwich used in standard LOCOS isolation. The presence of the intermediate poly layer allows the oxide to be thinned and nitride thickened without generating undue stress in active regions in order to reduce encroachment during field oxidation. Lateral encroachment is reduced to approximately 0.1 μm/side for PBL, compared to 0.5 μm/side for standard LOCOS. The effectiveness of this polysilicon cushion layer was proven by defect etching as well as by electrical measurements of gate oxide integrity (GOI) breakdown voltage and other critical device parameters such as diode leakage, transistor Vt and subthreshold slope, and parasitic field oxide threshold. Process details and electrical characterizations obtained during the implementation of poly‐buffered LOCOS are reported. Considerable process latitude exists in buffer layer thickness and dry or wet removal techniques, demonstrating the production tolerance of PBL.

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Section: Discussionmentioning

confidence: 99%

Section: Electrical Characterizationmentioning

confidence: 99%

Section: Electrical Characterizationmentioning

confidence: 99%

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Characterization of Poly‐Buffered LOCOS in Manufacturing Environment

Guldi

McKee

Damminga

et al. 1989

J. Electrochem. Soc.

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“…Using a stress relief layer of polysilicon between the oxide and silicon nitride layers, the lateral encroachment of the field oxide into the active area has been reduced to a value below 0.1 pm per side for a 0.8-pm CMOS technology [2].…”

Section: Introductionmentioning

confidence: 99%

Boron channel-stop design for poly-buffered LOCOS using selective boron segregation

Pfiester

1989

IEEE Electron Device Lett.

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A novel boron cbannel-stop compensation technique using a selective poly etch prior to field oxidation is proposed for CMOS isolation technologies wbicb use poly-buffered LOCOS (PBL). Tbe stress relief polysilicon layer is selectively removed over the n-well field regions wbicb results in additional boron segregation into the growing field oxide while the polysllicon layer is W i g oxidized over tbe p-well field regions. The resulting field tbresbold voltage$ are increased by as much as 11.6 and 6.4 V for the p-well and n-well MOS eapncitors, respectively.

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“…The via had a 0.3 µm diameter, and it was filled with blanket chemical vapor deposition (CVD) tungsten 22). In our 0.25-µm-rule BiCD process, the tungsten-filled via was introduced because it is a solution to the problems of metallization such as insulator layer planarization and contact failure [22][23][24][25]. Furthermore, the tungsten-filled via and the aluminum wire layers are electrically connected with higher reliability than the copper or aluminum plug [26][27][28].…”

mentioning

confidence: 99%

Reliability study of thermal cycling stress on smart power devices

Zhang

Yoshihisa

Furuya

et al. 2014

Jpn. J. Appl. Phys.

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In this paper, we describe a smart power device degradation behavior under thermal cycling stress. An innovative test structure was developed, which faithfully reflects a stress state caused by the smart power device during operation. From our experiment, the device degraded after millions of fast thermal cycling pulses. We discovered that via destruction was the cause of the device degradation. For the duration of thermal cycling stress, the via resistance increased gradually, and finally increased rapidly at the point of millions of cycles. A failure via was observed, which was broken into two parts. Therefore, the via disconnection was considered to be due to thermo-mechanical stress or electro-migration. Some experiments were conducted, and we demonstrated that the via destruction dominated to the thermo-mechanical stress introduced by the thermal cycling stress.

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An 0.8&#181;m CMOS technology for high performance logic applications

Cited by 23 publications

References 2 publications

Characterization of Poly‐Buffered LOCOS in Manufacturing Environment

Characterization of Poly‐Buffered LOCOS in Manufacturing Environment

Boron channel-stop design for poly-buffered LOCOS using selective boron segregation

Reliability study of thermal cycling stress on smart power devices

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