Boron channel-stop design for poly-buffered LOCOS using selective boron segregation

Abstract

A novel boron cbannel-stop compensation technique using a selective poly etch prior to field oxidation is proposed for CMOS isolation technologies wbicb use poly-buffered LOCOS (PBL). Tbe stress relief polysilicon layer is selectively removed over the n-well field regions wbicb results in additional boron segregation into the growing field oxide while the polysllicon layer is W i g oxidized over tbe p-well field regions. The resulting field tbresbold voltage$ are increased by as much as 11.6 and 6.4 V for the p-well and n-well MOS eapncitors, respectively.