<tex>$1/f$</tex>Noise and Generation/Recombination Noise in SiGe HBTs on SOI

Low-frequency noise in downscaled silicon transistors: Trends, theory and practice

“…The second factor for deviation of noise level around the trend in Figure 2 can be attributed to differences in the fabrication of BJT. The impact of several technology steps on the low-frequency noise in polysilicon emitter BJTs was reviewed several times, for example in [31], and extensively analyzed in the past [18,19,20,21,32,33,34,35,36,37,38,39,40]. From these studies, it is found that among the many sources that can contribute to the low-frequency noise, such as fluctuation in diffusion, surface recombination and charge trapping, the major noise source is associated with or located in the interfacial oxide (IFO) between poly and monosilicon layers in the emitter of BJT.…”

“…Typical types of cross-over in the noise in BJT are between areal and peripheral noise sources in the emitter region [14,21,35,36,42,60], noise from tunneling through IFO and series resistances (carrier number fluctuation, or coupled noise to the injection process, precisely) and diffusion noise (mobility fluctuation, or intrinsic noise of the current flow in emitter and base regions) [10,19,21,32,42,61,62], surface and bulk noise sources [14,21,24,36,37,42,60], and for very small-area BJTs (A E ≤0.1µm 2 ), the extension length of the base to the contact via becomes an issue for the low-frequency noise [36,37], since that extension is with large area compared to A E , and it is vulnerable to the surface noise from the oxide on the top of the structure. Also, in small-area BJTs, the crossover between generation-recombination (GR), random telegraph signal (RTS) and 1/f noise becomes apparent [11,12,17,18,30,35,63]. The identification of noise sources uses many techniques, such as noise partitioning (or decomposition the total noise in several components), superposition of noise components, evolution of noise components and correlation between them with bias, area and perimeter of the emitter, fitting to physical models and equivalent circuits.…”

A Theoretical Study of Low Power Soi Technology

“…The active elements (e.g., transistors in a CMOS IC) of semiconductor devices are fabricated in the single-crystal silicon surface layer over the BOX. [2,1] The BOX layer provides robust vertical isolation from the substrate. Standard LOCOS (Local Oxidation of Silicon) or STI (Shallow Trench Isolation) processes are employed to provide lateral isolation from adjacent devices.…”

Silicon on Insulator Technology Review

“…Consequently, the SOI CMOS circuits typically demonstrate higher speed performance and lower power dissipation than bulk or epitaxial CMOS. Also, the SOI CMOS device exhibits several parasitic phenomena that are not typically observed in the bulk or epitaxial CMOS device [5,6,132].…”

“…[132,131] The BOX layer provides robust vertical isolation from the substrate. Standard LOCOS (Local Oxidation of Silicon) or STI (Shallow Trench Isolation) processes are employed to provide lateral isolation from adjacent devices.…”