Amorphous silicon anti-fuse for high-speed FPGA application

Jain, Vivek; Nariani, S.R.; Gabriel, Calvin T.; Boardman, William J.; Chan, D.S.H.; Chang, Kow–Ming; Gordon, Keith E.; Wong, Richard

doi:10.1109/asic.1992.270296

Cited by 7 publications

(1 citation statement)

References 5 publications

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“…Programmable devices such as programmable read-only memories (PROMs) [1][2][3][4][5] and field-programmable gate arrays (FPGAs) [5][6][7][8][9][10] have been used as the instruction memory in digital systems for rapid implementation of the systems. As a candidate for a low-voltage PROM for on-chip programmable devices, a novel MOS PROM using a fusible link as a memory element was suggested [4,5].…”

Section: Introductionmentioning

confidence: 99%

A novel BaTiO₃/SiO₂-based voltage-programmable link applicable to on-chip programmable devices

Lee

Bae

Lee

2000

Semicond. Sci. Technol.

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A novel voltage-programmable link (VPL) with Al/BaTiO 3 /SiO 2 /TiW silicide/TiW structure has been developed for programmable device application. A programming cell to evaluate programming behaviour consists of an n-MOSFET and a VPL, which are connected in series. The programming process of the VPL was achieved through the switched n-MOSFET. The amorphous BaTiO 3 film, prepared by means of an RF sputtering method, determines the program properties of the VPL owing to its lower breakdown field and metallic components. Sufficient low on resistance less than 10 and low programming voltage below 10 V can be realized by using BaTiO 3 (120 Å)/SiO 2 (150 Å) films as insulators while keeping sufficient off-state reliability.

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Section: Introductionmentioning

confidence: 99%

A novel BaTiO₃/SiO₂-based voltage-programmable link applicable to on-chip programmable devices

Lee

Bae

Lee

2000

Semicond. Sci. Technol.

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OTP Memory for Low Cost Passive RFID Tags

Lee

Barsatan

Chan

2007

2007 IEEE Conference on Electron Devices and Solid-State Circuits

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CMOS-compatible zero-mask One Time Programmable (OTP) memory design

Chan

Lee

et al. 2008

2008 9th International Conference on Solid-State and Integrated-Circuit Technology

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Figure 1. Schematic of cross-point memory structure based on (a) simple switch and (b) with the addition of PN diodes in series 2.2 Programming of diode based OTP memoryThe schematic of a back-to-back diode OTP memory is given in Fig. 2 and the corresponding voltages used in program and disable are summarized in table 1. During programming, the program wordline of the selected row of the memory array is pulled up to a high voltage, while those unselected rows are either grounded or left at a high impedance state. The reverse-bias diode in cell D will be broken down to become a resistor [5]-[6]. on

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Amorphous silicon anti-fuse for high-speed FPGA application

Cited by 7 publications

References 5 publications

A novel BaTiO₃/SiO₂-based voltage-programmable link applicable to on-chip programmable devices

A novel BaTiO₃/SiO₂-based voltage-programmable link applicable to on-chip programmable devices

OTP Memory for Low Cost Passive RFID Tags

CMOS-compatible zero-mask One Time Programmable (OTP) memory design

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Amorphous silicon anti-fuse for high-speed FPGA application

Cited by 7 publications

References 5 publications

A novel BaTiO3/SiO2-based voltage-programmable link applicable to on-chip programmable devices

A novel BaTiO3/SiO2-based voltage-programmable link applicable to on-chip programmable devices

OTP Memory for Low Cost Passive RFID Tags

CMOS-compatible zero-mask One Time Programmable (OTP) memory design

Contact Info

Product

Resources

About

A novel BaTiO₃/SiO₂-based voltage-programmable link applicable to on-chip programmable devices

A novel BaTiO₃/SiO₂-based voltage-programmable link applicable to on-chip programmable devices