All-CMOS High-Speed CML Gates with Active Shunt-Peaking

We present the design and test results of two optical data transmission ASICs for the High-Luminosity LHC (HL-LHC) experiments. These ASICs include a two-channel serializer (LOCs2) and a single-channel Vertical Cavity Surface Emitting Laser (VCSEL) driver (LOCld1V2). Both ASICs are fabricated in a commercial 0.25-μm Silicon-on-Sapphire (SoS) CMOS technology and operate at a data rate up to 8 Gbps per channel. The power consumption of LOCs2 and LOCld1V2 are 1.25 W and 0.27 W at 8-Gbps data rate, respectively. LOCld1V2 has been verified meeting the radiation-tolerance requirements for HL-LHC experiments.

Section: The Design Of Locs2mentioning

confidence: 99%

Optical data transmission ASICs for the high-luminosity LHC (HL-LHC) experiments

Liu

Chen

et al. 2014

“…Even with multi-stage structure, we still have to use a bandwidth extension technique. We choose the shunt peaking technique [13][14]. Since we cannot afford a pair of embedded spiral inductors (250 μm  250 μm in the process we use) for each stage, we choose the active shunt peaking technique.…”

Section: Div2mentioning

confidence: 99%

Update on the high speed serializer ASIC development for ATLAS Liquid Argon calorimeter upgrade

Liu

2011

We have been developing a serializer application-specific integrated circuit (ASIC) based on a commercial 0.25-μm silicon-on-sapphire (SOS) CMOS technology for the ATLAS liquid argon calorimeter front-end electronics upgrade. The first prototype, a 5 Gbps 16:1 serializer has been designed, fabricated, and tested in lab environment and in a 200 MeV proton beam. The test results indicate that the first prototype meets the design goals. The second prototype, a double-lane, 8 Gbps per lane serializer is under development. The post-layout simulation indicates that 8 Gbps is achievable. In this paper we present the design and the test results of the first prototype and the design and status of the second prototype. KEYWORDS: VLSI circuits; Analogue electronic circuits; Front-end electronics for detector readout. 2.1 The design 1 2.2 The lab test 2 2.3 The radiation test 3 2.4 The LCPLL 4 3. The design and test of a single-lane serializer 5 3.1 The design of the double-lane serializer 1 3.2 The design of the laser driver array 2 4. Conclusion 5

“…The driver has seven stages, providing enough gain as well as large bandwidth. Active shunt-peaking uses smaller active inductors instead of the on-chip passive inductors [9]. A resistor and a NMOS transistor where the resistor is in series with the gate of the transistor can function as an active inductor.…”

Section: Introductionmentioning

confidence: 99%

8-Gbps-per-channel radiation-tolerant VCSEL drivers for the LHC detector upgrade

Guo

Chen

et al. 2015

We present ASIC designs of VCSEL drivers for a single VCSEL (LOCld1), two individual VCSELs (LOCld2) and a four-channel VCSEL array (LOCld4). This work is for new detector readout systems needed in the Large Hadron Collider upgrade program. All ASICs are fabricated in a commercial 0.25-µm Silicon-on-Sapphire CMOS technology. LOCld1 and LOCld2 have passed the 8-Gbps and 10-Gbps eye mask tests. Operating at 8 Gbps data rate, the measured total jitter of LOCld1 and LOCld2 is less than 30 ps, and the power comsuption is about 200 mW per channel with 6-mA bias current and 6.4-mA modulation current. The radiation tolerance of LOCld1 has been qualified with x-ray and high-energy neutron beam test.